xsim

PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities

Vivado MCP server — 让 Claude Code / Cursor / Codex 驱动本地 FPGA 全流程。30 个精选工具、8 个证据驱动 Prompt、doctor 环境自检、GUI/Tcl/attach 会话，以及时序和 CRITICAL WARNING 中文诊断。

USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL

10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL

Convert Vivado/VCD/XSim WDB and WCFG waveform databases directly to VCD, CSV, JSON and Excel. GUI, batch conversion, signal filtering and radix controlls.

Vivado Simulator (XSim) xvlog/xvhdl plugin for SublimeLinter. Linting for Verilog/SystemVerilog and VHDL.

Logic Expression Compiler, with Logic Minimization, to NAND/NOR Implementation

A verified four-stage RV32I pipeline with parameterized L1 instruction/data caches, XSim regression tests, and portable Vivado flows.

This project implements AXI-based matrix multiply accelerator.

This repository showcases my hands-on SystemVerilog UVM verification using Xilinx Vivado XSIM, focusing on real-world RTL verification, debugging, coverage, and regression scenarios.

Project is a high-precision chronometer using VHDL, intended for implementation on an FPGA. The chronometer is designed to operate with nanosecond (ns) precision and is capable of accurately measuring elapsed time in milliseconds, seconds, and minutes. The design has been tested using a VHDL test bench and verified with the XSim extensively.

The PWM (Pulse Width Modulation) Generator creates a PWM signal to control PWM-driven devices. It allows configurable clock and PWM frequencies via generics. The duty cycle, input as a 7-bit signal, adjusts the proportion of time the signal is high.

Simple UVM example with Altair (Metrics) DSim and Vivado xsim

UVM 1.2 functional verification environment for ARMv8-M PACBTI, TrustZone, privilege faults, and AHB-Lite behavior

HSpecID-X: A Hyperspectral Pixel Classifier Accelerator for X-HEEP

SystemVerilog AXI4-Lite protocol verification environment featuring a 5-channel monitor, associative-array scoreboard, 13 SVA assertions, functional coverage closure, back-pressure testing, and negative protocol testbench.