Skip to content
View marslan6's full-sized avatar
18 followers · 12 following
  • Munich, Bavaria, Germany
  • 02:51 (UTC +02:00)
  • LinkedIn in/htmos6

Achievements

Achievement: Pull Sharkx3Achievement: YOLOAchievement: Quickdraw

Achievements

Achievement: Pull Sharkx3Achievement: YOLOAchievement: Quickdraw

Highlights

  • Pro

Block or report marslan6

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
marslan6/README.md

Hi there! 👋 I'm Mehmet Arslan

I am an Embedded Software & FPGA Engineer based in Munich, Germany.

  • 🎓 M.Sc. in Communications & Electronics — Technical University of Munich (Munich, Germany)
  • 🎓 B.Sc. in Electrical & Electronics Engineering — Middle East Technical University (Ankara, Turkey)

🔧 Skills

HDL & Verification

VHDL Verilog SystemVerilog UVM OSVVM Cocotb

FPGA & ASIC Tools

Vivado Quartus ModelSim Design Compiler Xcelium RISC-V

Languages

C C++ Python

RTOS & Platforms

FreeRTOS Zephyr VxWorks Embedded Linux ARM

Toolchain

Keil VS Code CMake GNU Make GDB Git

💼 Expertise

FPGA Design & Verification

  • RTL design in VHDL, Verilog and SystemVerilog
  • RISC-V / MIPS processor implementations
  • Verification with UVM and Cocotb
  • Synthesis and simulation
  • Timing closure, Route & Placement and resource optimization

Embedded Systems

  • Arm Cortex-M/A firmware — bare-metal and RTOS
  • VxWorks, FreeRTOS, Zephyr and Embedded Linux
  • Peripheral and device drivers: UART, SPI, I²C, CAN, DMA, timers, ADC
  • Interrupt handling, scheduling and real-time constraint analysis
  • Bootloaders, memory maps, linker scripts and firmware update flows
  • On-target debugging with JTAG/SWD, GDB
  • Build and debug tooling: CMake, GNU Make, GDB, GCC, Clang

📫 Connect

LinkedIn GitHub

Pinned Loading

  1. Risc-V Risc-V Public

    A modular RV32I RISC-V processor core implemented in VHDL for FPGA synthesis and simulation. Project implements a single-cycle, non-pipelined RISC-V processor based on the RV32I base integer instru…

    VHDL

  2. MORSE-ENCODER MORSE-ENCODER Public

    A real-time Morse code encoder implementation for the XMC4500 ARM Cortex-M4 microcontroller. This project converts ASCII text strings into visual Morse code signals using precise timing control via…

    C

  3. ARM-Pipelined-Processor-With-Branch-Predictor ARM-Pipelined-Processor-With-Branch-Predictor Public

    A 32-bit ARM Pipelined Processor Implementation in Verilog HDL along with Forwarding, Hazard Detection, Handling and a Branch Predictor.

    Verilog 8

  4. Hide-Password Hide-Password Public

    Hardware-based timing side-channel attack for password extraction using XMC4500 ARM Cortex-M4. Exploits keystroke timing variations in password validation systems via USB HID keyboard emulation.

    C

  5. ARM-Processor-Designs ARM-Processor-Designs Public

    Repository with single-cycle, multi-cycle, and pipelined processor designs for architecture labs. Enables study and experimentation to understand processor functionality and performance improvemen…

    Verilog

  6. Flancter Flancter Public

    VHDL implementation of the Flancter circuit, a cross-clock-domain handshake mechanism for generating and clearing interrupt requests between an FPGA and microprocessor, featuring toggle-based set/c…

    VHDL