testbench-generation

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BakxY / VHDL-QQS

VS Code extension for Intel Quartus: seamless project compilation, direct access to the Quartus programmer and RTL viewer, automated testbench generation for QuestaSim, integrated QuestaSim simulation, streamlined project configuration, direct file management, top-level entity changes, and on-demand source file formatting.

open-source typescript fpga simulation vhdl vscode visual-studio-code vscode-extension questasim quartus intel-fpga testbench-generation

Updated May 14, 2026
TypeScript

Sawaiz-zip / agentic-verilog-testbench

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Agentic Verilog testbench generation: a LangGraph multi-agent pipeline that writes HDL testbenches from natural language, catches structural faults with Pyverilog static analysis before simulation, and repairs them from structured feedback. 93% fault detection, measured by fault injection.

static-analysis eda verilog hdl pyverilog hardware-verification llm-agents langgraph agentic-ai testbench-generation

Updated Sep 24, 2026
Python

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