interconnect

Parametric AXI4 crossbar in SystemVerilog

A Chisel RTL generator for network-on-chip interconnects

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

AHB3-Lite Interconnect

Tartan: Evaluating Modern GPU Interconnect via a Multi-GPU Benchmark Suite

RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction.

Cross-instance message/event handoff plugins for DSH (interconnect service + tools)

The central repository for the Cosmia project, containing the core architecture and infrastructure for the Sidra Chain.

Fork of the gem5 simulator with Garnet2.0 and DSENT extensions

Offline First demo app for IBM InterConnect 2017

The Interoperable Recommender is a data-driven solution aimed at enabling the participation of consumers in enhancing the resilience of the European energy infrastructure.

OpenShift S2I image/templates and accompanying test suite showcasing various AMQ7 broker/router topologies.

Open source AXI4 / AXI4-Lite interconnect generator. Describe your bus topology in YAML, get you Verilog back

A humble exploratory PoC for a hardware-native, optical timing-frozen control plane engine. Fuses inline CUDA PTX, RAII memory tunnels, and 4D JAX shard_map structures to investigate 0ns-overhead fault-tolerant routing for hyperscale distributed AI.

Test suite showcasing various AMQ 7 Reference Architecture broker/router topologies on OpenShift

3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.

VHDL implementation of Pipelined Wishbone B4 interconnect

SystemVerilog AXI4/AXI4-Lite RTL library

Scaling AMQ 7 Brokers with AMQ Interconnect

Dynamic Incentives for Electric Vehicles Charging: Causal Insights on Demand Flexibility