axi_lib

axi_lib is a SystemVerilog AXI RTL library for FPGA/ASIC designs. It provides AXI4/AXI4-Lite/AXI4-Stream interconnect and function modules, plus primitive components (arbiter, sync/async FIFOs, skid buffer). Simulation uses Verilator with BFMs from vaxivip and coroutine engine from corosim.

✨ Features

AXI4, AXI4-Lite and AXI4-Stream functional modules
Parameterized design: flexible port count, address map and burst type configuration
Reusable primitive components: arbiter, FIFOs, skid buffer
Verilator-verified with C++ BFM testbenches
MIT licensed

🚀 Quick Start

1. Install Dependencies

# macOS (with Homebrew)
brew install verilator

# Ubuntu/Debian
sudo apt-get install verilator g++ make

2. Download Dependencies

python run.py init
# or: ./run.sh init

3. Run Simulation

# run all testbenches
python run.py sim

# run a specific testbench
python run.py sim axi_interconnect

# or using the shell wrapper
./run.sh sim

4. View Waveform (optional)

cd sim/tb/axi_interconnect
make waves    # requires gtkwave

📖 Project Structure

.
├── rtl/                        # RTL source
│   ├── if_axi.sv               # AXI4 interface (modport master/slave)
│   ├── if_axil.sv              # AXI4-Lite interface
│   ├── if_axis.sv              # AXI4-Stream interface
│   ├── axi_interconnect.sv     # AXI4 crossbar interconnect
│   ├── axil_interconnect.sv    # AXI4-Lite crossbar interconnect
│   ├── axi2axil.sv             # AXI4 to AXI4-Lite bridge
│   ├── axil2axi.sv             # AXI4-Lite to AXI4 bridge
│   ├── axil2reg_bridge.sv      # AXI4-Lite to register bridge
│   ├── axis_async_fifo.sv      # AXI4-Stream async FIFO
│   ├── arbiter.sv              # Priority arbiter
│   ├── sync_fifo.v             # Synchronous FIFO
│   ├── async_fifo.v            # Asynchronous FIFO
│   └── skid_buffer.v           # Pipeline skid buffer
├── .deps/                      # Auto-downloaded dependencies (gitignored)
│   ├── sim/vaxivip/            # BFM sources from vaxivip
│   ├── sim/corosim/            # Coroutine engine from corosim
│   └── rtl/                    # (future) external RTL dependencies
├── script/
│   ├── get_deps.py             # Dependency downloader
│   ├── remove_trailing_spaces.py
│   └── file_list.py
├── run.py                      # Project entry point
├── run.sh                      # Shell wrapper for run.py
├── sim/
│   └── tb/                     # Testbenches
│       ├── axi_interconnect/   # AXI4 crossbar TB
│       ├── axil_interconnect/  # AXI4-Lite crossbar TB
│       ├── axi2axil/           # AXI4 to AXI4-Lite bridge TB
│       ├── axil2axi/           # AXI4-Lite to AXI4 bridge TB
│       ├── axilreg/            # AXI4-Lite register bridge TB
│       └── axis_async_fifo/    # AXI4-Stream async FIFO TB (uses corosim)
└── README.md

🧩 RTL Modules

Module	Protocol	Description
`axi_interconnect` (`rtl/axi_interconnect.sv`)	AXI4	Configurable multi-master multi-slave crossbar with arbitration, optional per-port input/output FIFO buffering, address decode routing
`axil_interconnect` (`rtl/axil_interconnect.sv`)	AXI4-Lite	Configurable multi-master multi-slave crossbar with arbitration, optional per-port skid buffer, address decode routing
`axi2axil` (`rtl/axi2axil.sv`)	AXI4 → AXI4-Lite	Burst-to-single-beat bridge, supports FIXED/INCR/WRAP, single outstanding transaction
`axil2axi` (`rtl/axil2axi.sv`)	AXI4-Lite → AXI4	Single-beat bridge, maps AXI4-Lite to AXI4 len=0 transactions

Module Structure

axi_interconnect — per-master decode → matrix → per-slave arbiter + buffer

  AW ─► [skid] ─► decoder ─┐  ┌──────┐  ┌── arbiter ─► [skid] ─► AW
  W  ─► [FIFO] ────────────├──│matrix│──┤── mux     ─► [FIFO] ─► W
                           │  └──────┘  │
  B  ◄─ [skid] ◄───────────┘            └── demux   ◄─ [skid] ◄─ B

  AR ─► [skid] ─► decoder ─┐  ┌──────┐  ┌── arbiter ─► [skid] ─► AR
                           ├──│matrix│──┤
  R  ◄── [FIFO] ◄──────────┘  └──────┘  └── demux   ◄─ [FIFO] ◄── R

decoder: AW/AR address decode → determines target slave; W/B/R flow is gated by register-based burst tracking
arbiter (AW/AR): per-slave fixed-priority arbitration across competing masters
demux (B/R): ID-embedded response routing back to correct master
mux (W): follows current arbiter grant, single-cycle

axil_interconnect — tracking FIFOs replace register tracking, multi-outstanding

  AW ─► [skid] ─► decoder ─┐  ┌──────┐  ┌── arbiter ──► [skid] ─► AW
  W  ─► [skid] ── wtrk  ───├──│matrix│──┤── awgnt   ──► [skid] ─► W
                           │  └──────┘  │
  B  ◄─ [skid] ── btrk  ◄──┘            └── btrk   ◄─── [skid] ◄─ B

  AR ─► [skid] ─► decoder ─┐  ┌──────┐  ┌── arbiter ──► [skid] ─► AR
                           ├──│matrix│──┤
  R  ◄─ [skid] ── rtrk  ◄──┘  └──────┘  └── rtrk   ◄─── [skid] ◄─ R

wtrk/btrk/rtrk: tracking FIFOs per-channel, store target slave / grant vector per outstanding transaction (TRK_DEPTH)
awgnt: stores arbiter grant, routes W data to the winning master
skid: all channels use register-based 2-deep elastic buffer (zero BRAM)
Tracking FIFO RAM style configurable via TRK_RAM_STYLE

🧪 Testbench

Simulation uses C++ BFMs from vaxivip and a coroutine engine from corosim. Dependencies are auto-downloaded via python run.py init. The BFMs follow an update_input() → eval() → update_output() pattern for clock-edge-accurate signal timing.

Simulation Loop

top->clk = 1;
top->eval();

// negedge: sample DUT outputs
axi_mst.update_input();
axi_slv.update_input();

top->clk = 0;
top->eval();

if (top->clk) {
    // posedge: initiate transactions
    if (cycle == 10) axi_mst.write_incr(0x1000, {0xAA, 0xBB});
}

// posedge: drive DUT inputs
axi_mst.update_output();
axi_slv.update_output();

BFM Modules

Module	Protocol	Description
`axi` (`.deps/sim/vaxivip/axi/`)	AXI4	Master/Slave interface supporting FIXED, INCR, WRAP burst
`axil` (`.deps/sim/vaxivip/axil/`)	AXI4-Lite	Master/Slave interface
`axis` (`.deps/sim/vaxivip/axis/`)	AXI4-Stream	Master/Slave interface
`corosim` (`.deps/sim/corosim/`)	C++20 coroutine	Cooperative simulation engine for pipelined protocols

See sim/tb/axi_interconnect/axi_interconnect_tb.cpp and sim/tb/axis_async_fifo/axis_async_fifo_tb.cpp for examples.

📝 Acknowledgements

Design references axi-crossbar.

📄 License

MIT License

axi_lib

axi_lib 是一个 SystemVerilog AXI RTL 库，适用于 FPGA/ASIC。提供 AXI4/AXI4-Lite/AXI4-Stream 互连与功能模块，以及仲裁器、FIFO、skid buffer 等基础组件。仿真采用 Verilator，BFM 来自 vaxivip，协程引擎来自 corosim。

✨ 特性概览

提供 AXI4、AXI4-Lite、AXI4-Stream 相关的功能模块
参数化设计：灵活配置端口数量、地址映射和突发类型
内置仲裁器、FIFO、skid buffer 等基础组件，可独立复用
Verilator 验证，配套 C++ BFM 测试平台
MIT 许可

🚀 快速开始

1. 安装依赖

# macOS (使用 Homebrew)
brew install verilator

# Ubuntu/Debian
sudo apt-get install verilator g++ make

2. 下载依赖

python run.py init
# 或：./run.sh init

3. 运行仿真

# 仿真全部 testbench
python run.py sim

# 仿真指定 testbench
python run.py sim axi_interconnect

# 或使用 shell 包装脚本
./run.sh sim

4. 查看波形（可选）

cd sim/tb/axi_interconnect
make waves    # 需要 gtkwave

📖 项目结构

.
├── rtl/                        # RTL 源代码
│   ├── if_axi.sv               # AXI4 接口
│   ├── if_axil.sv              # AXI4-Lite 接口
│   ├── if_axis.sv              # AXI4-Stream 接口
│   ├── axi_interconnect.sv     # AXI4 交叉开关互连
│   ├── axil_interconnect.sv    # AXI4-Lite 交叉开关互连
│   ├── axi2axil.sv             # AXI4 转 AXI4-Lite 桥接器
│   ├── axil2axi.sv             # AXI4-Lite 转 AXI4 桥接器
│   ├── axil2reg_bridge.sv      # AXI4-Lite 寄存器桥接器
│   ├── axis_async_fifo.sv      # AXI4-Stream 异步 FIFO
│   ├── arbiter.sv              # 优先级仲裁器
│   ├── sync_fifo.v             # 同步 FIFO
│   ├── async_fifo.v            # 异步 FIFO
│   └── skid_buffer.v           # 流水线缓冲器
├── .deps/                      # 自动下载的依赖（已忽略 git）
│   ├── sim/vaxivip/            # BFM 源文件（来自 vaxivip）
│   ├── sim/corosim/            # 协程引擎（来自 corosim）
│   └── rtl/                    # （预留）外部 RTL 依赖
├── script/
│   ├── get_deps.py             # 依赖下载脚本
│   ├── remove_trailing_spaces.py
│   └── file_list.py
├── run.py                      # 项目入口
├── run.sh                      # run.py 的 shell 包装
├── sim/
│   └── tb/                     # 测试用例
│       ├── axi_interconnect/   # AXI4 交叉开关测试
│       ├── axil_interconnect/  # AXI4-Lite 交叉开关测试
│       ├── axi2axil/           # AXI4 转 AXI4-Lite 桥接测试
│       ├── axil2axi/           # AXI4-Lite 转 AXI4 桥接测试
│       ├── axilreg/            # AXI4-Lite 寄存器桥接测试
│       └── axis_async_fifo/    # AXI4-Stream 异步 FIFO 测试（使用 corosim）
└── README.md

🧩 RTL 模块

模块	协议	功能描述
`axi_interconnect` (`rtl/axi_interconnect.sv`)	AXI4	主机/从机数量可配置的多路仲裁交叉开关，每端口可选输入/输出 FIFO 缓冲，地址译码路由到对应从机
`axil_interconnect` (`rtl/axil_interconnect.sv`)	AXI4-Lite	主机/从机数量可配置的多路仲裁交叉开关，每端口可选 skid buffer 缓冲，地址译码路由到对应从机
`axi2axil` (`rtl/axi2axil.sv`)	AXI4 → AXI4-Lite	突发转单拍桥接器，支持 FIXED/INCR/WRAP，单笔 outstanding
`axil2axi` (`rtl/axil2axi.sv`)	AXI4-Lite → AXI4	单拍桥接器，AXI4-Lite 映射为 AXI4 len=0 事务

模块结构

axi_interconnect — 每 master 译码 → matrix → 每 slave 仲裁 + 缓冲

  AW ─► [skid] ─► 译码器 ─┐  ┌──────┐  ┌── 仲裁器 ─► [skid] ─► AW
  W  ─► [FIFO] ──────────├──│matrix│──┤── mux   ─► [FIFO] ─► W
                         │  └──────┘  │
  B  ◄─ [skid] ◄─────────┘            └── demux ◄─ [skid] ◄─ B

  AR ─► [skid] ─► 译码器 ─┐  ┌──────┐  ┌── 仲裁器 ─► [skid] ─► AR
                         ├──│matrix│──┤
  R  ◄─ [FIFO] ◄─────────┘  └──────┘  └── demux ◄─ [FIFO] ◄─ R

译码器：AW/AR 地址译码，确定目标从机；W/B/R 由寄存器实现的 burst 跟踪门控
仲裁器（AW/AR）：每从机固定优先级仲裁
demux（B/R）：ID 位解复用，响应路由回正确 master
mux（W）：跟随当前仲裁器 grant，单周期

axil_interconnect — 跟踪 FIFO 替代寄存器跟踪，支持多 outstanding

  AW ─► [skid] ─► 译码器 ─┐  ┌──────┐  ┌── 仲裁器 ──► [skid] ─► AW
  W  ─► [skid] ── wtrk ──├──│matrix│──┤── awgnt ──► [skid] ─► W
                         │  └──────┘  │
  B  ◄─ [skid] ── btrk ◄─┘            └── btrk ◄─── [skid] ◄─ B

  AR ─► [skid] ─► 译码器 ─┐  ┌──────┐  ┌── 仲裁器 ──► [skid] ─► AR
                         ├──│matrix│──┤
  R  ◄─ [skid] ── rtrk ◄─┘  └──────┘  └── rtrk ◄─── [skid] ◄─ R

wtrk/btrk/rtrk：跟踪 FIFO 每通道独立，存储目标从机/grant 向量（TRK_DEPTH）
awgnt：存储仲裁器 grant，W 路由到获得仲裁的 master
skid：全通道 2 级寄存器弹性缓冲（零 BRAM）
跟踪 FIFO RAM 类型通过 TRK_RAM_STYLE 控制

🧪 测试平台

仿真使用 vaxivip 的 C++ BFM 和 corosim 的协程引擎驱动。依赖通过 python run.py init 自动下载。BFM 遵循 update_input() → eval() → update_output() 时序模式实现时钟沿对齐的信号采样与驱动。

仿真循环

top->clk = 1;
top->eval();

// 下降沿：采样 DUT 输出
axi_mst.update_input();
axi_slv.update_input();

top->clk = 0;
top->eval();

if (top->clk) {
    // 上升沿：发起事务
    if (cycle == 10) axi_mst.write_incr(0x1000, {0xAA, 0xBB});
}

// 上升沿：驱动 DUT 输入
axi_mst.update_output();
axi_slv.update_output();

BFM 模块

模块	协议	功能描述
axi（`.deps/sim/vaxivip/axi/`）	AXI4	Master/Slave 接口，支持 FIXED、INCR、WRAP 突发
axil（`.deps/sim/vaxivip/axil/`）	AXI4-Lite	Master/Slave 接口
axis（`.deps/sim/vaxivip/axis/`）	AXI4-Stream	Master/Slave 接口
corosim（`.deps/sim/corosim/`）	C++20 协程	适用于流水线协议的合作仿真引擎

完整示例请参考 sim/tb/axi_interconnect/axi_interconnect_tb.cpp 和 sim/tb/axis_async_fifo/axis_async_fifo_tb.cpp。

📝 致谢

参考了 axi-crossbar 的设计。

📄 版权说明

MIT License

Navigation Menu

Repository files navigation

axi_lib

✨ Features

🚀 Quick Start

1. Install Dependencies

2. Download Dependencies

3. Run Simulation

4. View Waveform (optional)

📖 Project Structure

🧩 RTL Modules

Module Structure

🧪 Testbench

Simulation Loop

BFM Modules

📝 Acknowledgements

📄 License

axi_lib

✨ 特性概览

🚀 快速开始

1. 安装依赖

2. 下载依赖

3. 运行仿真

4. 查看波形（可选）

📖 项目结构

🧩 RTL 模块

模块结构

🧪 测试平台

仿真循环

BFM 模块

📝 致谢

📄 版权说明

About

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Name		Name	Last commit message	Last commit date
rtl		rtl
script		script
sim/tb		sim/tb
.gitattributes		.gitattributes
.gitignore		.gitignore
LICENSE		LICENSE
README.md		README.md
run.py		run.py
run.sh		run.sh

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Repository files navigation

axi_lib

✨ Features

🚀 Quick Start

1. Install Dependencies

2. Download Dependencies

3. Run Simulation

4. View Waveform (optional)

📖 Project Structure

🧩 RTL Modules

Module Structure

🧪 Testbench

Simulation Loop

BFM Modules

📝 Acknowledgements

📄 License

axi_lib

✨ 特性概览

🚀 快速开始

1. 安装依赖

2. 下载依赖

3. 运行仿真

4. 查看波形（可选）

📖 项目结构

🧩 RTL 模块

模块结构

🧪 测试平台

仿真循环

BFM 模块

📝 致谢

📄 版权说明

About

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