Design verification and digital design engineer with an M.S. in Computer Systems Engineering from the University of Houston (May 2026, GPA 3.8/4.0). I write RTL in Verilog and SystemVerilog, and I verify it in simulation before it reaches hardware.

Currently looking for Design Verification, RTL Design, and Digital Design Engineer roles.

M.S. Computer and Systems Engineering — University of Houston (Aug 2024 – May 2026) · GPA: 3.8/4.0 Relevant coursework: Advanced Computer Architecture · Advanced Topics in Computer Architecture · Advanced Imaging Techniques

B.E. Information Technology — Osmania University (2020 – 2024) · Grade: A

Verification & RTL  |  Verilog · SystemVerilog · ModelSim · Intel Quartus Prime · Functional Verification · Testbench Design · RTL Design · FSM Design · Digital Logic

Computer Architecture & Circuits  |  Cache Design & Coherency Protocols · Instruction-Level Parallelism · Pipelining · VLSI · CMOS · LTSpice

Languages  |  Python · C++ · Java · JavaScript · SQL · HTML/CSS

Software  |  Django · Android SDK · Firebase · SQLite · Git

ROM-Based Access Control (FPGA) FSM-driven password authentication in synchronous Verilog RTL with a ROM-stored password and LFSR-based timing. Verified in ModelSim, then synthesized and tested on a DE0-CV FPGA. Verilog ModelSim Intel Quartus Prime FPGA RTL FSM

4×4 DRAM Design – VLSI Transistor-level 4×4 DRAM in 180nm — 1T cells, 2-to-4 decoders, sense amplifiers, and CMOS D flip-flop row buffers, with FSM control for destructive read, automatic write-back, and refresh. Simulated in LTSpice at 1.8 V / 1 fF / 10 ps. LTSpice CMOS VLSI Semiconductor Memory FSM

Algorithm Visualizer Full-stack Django application visualizing 9 classic algorithms — 5 sorting, 2 searching, and BFS/DFS graph traversal — each implemented from scratch. Python Django JavaScript HTML/CSS SQLite

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