Verilog • SystemVerilog • Digital Design • ASIC Flow • RISC-V
I'm an aspiring RTL Design & Verification Engineer, currently building my foundation across the full ASIC design spectrum — from digital logic and RTL coding to functional verification and the RTL-to-GDSII flow.
- 🔬 Focused on RTL Design, Functional Verification, and Digital Logic
- 🧩 Comfortable with Verilog / SystemVerilog, FSM design, and simulation-based debugging
- ⚙️ Learning the ASIC RTL-to-GDSII flow using industry EDA tools
- 🖥️ Exploring RISC-V processor design through hands-on RTL implementation
- 🐍 Using Python and Linux for engineering workflows and automation
- 🤖 Integrating AI-assisted engineering into my learning and debugging process
I'm early in my journey and building real, verifiable skills — not claiming professional industry experience.
| Stage | Description |
|---|---|
| 🧠 Digital Design | Boolean logic, combinational & sequential circuits |
| ✍️ RTL Design | Verilog / SystemVerilog coding of digital modules |
| Functional simulation using ModelSim / EDA Playground | |
| ✅ Functional Verification | Testbenches, self-checking environments, waveform debug |
| 🔧 Synthesis | RTL-to-gate-level using Cadence Genus |
| ⏱️ STA | Static Timing Analysis for timing closure |
| 🏗️ Physical Design | Floorplanning, placement, CTS, routing using Cadence Innovus |
| 📦 GDSII | Final signoff layout for fabrication |
🔹 RTL Design
🔹 Verification
🔹 ASIC Design Flow
🔹 EDA Tools
🔹 Programming / Environment
I use these tools to speed up learning, documentation, debugging assistance, and everyday engineering workflows. They support my understanding of RTL and verification concepts — they don't replace hands-on simulation, waveform analysis, or hardware reasoning.
- 🧩 32-bit RV32IM RISC-V processor designed in Verilog HDL
- 🏭 Complete ASIC RTL-to-GDSII flow implementation
- 🛠️ Built using Cadence EDA tools (Genus, Innovus, NCLaunch)
- 🔬 Targeted at 7-nm technology node
- ⏱️ Focus on timing closure, area optimization, and power efficiency
- 📄 Published as an IEEE research paper
📚 IEEE Xplore: Design and Physical Implementation of an RV32IM RISC-V Core in 7-nm Technology Using Cadence EDA Flow
- ➕ Arithmetic operations (add, subtract, multiply)
- 🔣 Logical operations (AND, OR, XOR, NOT)
- ⚖️ Comparison operations
↔️ Shift operations (logical & arithmetic)- 🧩 Fully parameterized RTL design
- ✅ Self-checking Verilog testbench
▶️ RTL simulation, debugging, and functional verification
|
🔌 UART Protocol RTL design and verification of a UART transmitter/receiver with testbench-based functional checks. |
🔁 FSM Design & Verification Finite state machine modeling in RTL with simulation-based verification of state transitions. |
|
🔢 Counters Parameterized synchronous/asynchronous counter designs verified through simulation. |
📥 FIFO FIFO buffer design with functional verification of read/write pointers and flag conditions. |
|
🧠 RAM / Memory Design RTL memory module design with read/write verification. |
🚌 APB-based Memory APB protocol interfacing with memory blocks, verified via testbench simulation. |
|
⏰ Clock / Frequency Generation RTL modules for clock division and frequency generation, verified through simulation. |
|
Digital Logic → Verilog → RTL Design → FSM → Memory → FIFO → UART → APB → SystemVerilog → Verification → ASIC Flow → RISC-V
This reflects a progressive learning path, not claimed professional experience — each stage represents concepts and skills built through coursework, self-study, and hands-on projects.
✅ Hands-on experience: RTL Design, Simulation, Synthesis (Cadence Genus), Physical Design flow using Cadence Innovus (via academic project/workshop) 📖 Currently learning: Advanced STA, full-chip physical design signoff, and verification methodology (UVM concepts)
- 📘 SystemVerilog (advanced constructs)
- ✍️ Advanced RTL Design
- ✅ Functional Verification methodology
- 🔁 FIFO / CDC (Clock Domain Crossing) concepts
- 🚌 APB / UART protocol design
- 🏭 ASIC design flow (deeper physical design)
- 🖥️ RISC-V architecture
- 🧪 Verification methodology fundamentals
- 📋 Understand the specification before coding.
- ⏱️ Design RTL with clear timing behavior.
- ✅ Verify functionality, not just compilation.
- 🌊 Debug from waveform evidence.
- 🎯 Think about corner cases.
- 🏭 Understand the complete ASIC flow.
- 🤖 Use AI as an engineering assistant, not as a replacement for understanding.
B.Tech — Electronics and Communication Engineering
Madanapalle Institute of Technology & Science (MITS), Deemed to be University
2022 – 2026 | CGPA: 8.19/10
- 🏗️ Physical Design (RTL-to-GDSII) Workshop — KT Semicon, 2026
- 🔬 VLSI SoC Design using Verilog HDL — Maven Silicon, 2025
- 💻 Introduction to Microprocessors — edX
- ⚡ VLSI Training — NIELIT, 2025
- 🐍 Python for Beginners — Simplilearn