Plugins for Yosys developed as part of the F4PGA project.
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Updated
May 14, 2024 - Verilog
Plugins for Yosys developed as part of the F4PGA project.
A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad
Yosys passes to syntheize to NaN gates (à la http://tom7.org/nand/)
A design space exploration tool for approximate circuits
This repository contain source code for new flow of FreeEDA now know as eSim
OpenSTA network adapter for Yosys
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