veryl

RV64IMAC_Ziscr_Zicntr + UART

A tiny CPU written in Veryl

developing NES on FPGA project.

ADAT Receiver RTL

A detour into hardware programming for Advent of Code 2025.

ruskcore - A RISC-V CPU written in Veryl.

This repository has been moved to https://github.com/Ryoga-exe/cojt-hw/tree/main/dounyu

ComProc CPU ボード (Tang Nano 9K) の LCD に hello, world を表示する回路を Veryl で実装

a veryl dev template repo with a docker container for working with veryl and rggen

Uart implementation for FPGA with veryl.

University of Tsukuba COJT Embedded Systems OJT Hardware Course assignments

This repository has been moved to https://github.com/Ryoga-exe/cojt-hw/tree/main/pattern

RV32IMA_Zicsr written in Veryl running on Tang Primer 20K

A Veryl port of micro-alpha

Veryl + open-source FPGA toolchain playground for Tang Nano 9K (GW1NR-9C)

RISC-V processor made in Veryl