systemrdl-compiler

SystemRDL 2.0 language compiler front-end

Control and status register code generator toolchain

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Generate address space documentation HTML from compiled SystemRDL input

Import and export IP-XACT XML register models

C++ 17 Hardware abstraction layer generator from systemrdl

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.

Semantic compatibility analysis and configurable quality gates for SystemRDL specifications. Detects firmware-breaking register changes, produces CI reports and provides scalable exploration of large register maps.

This repository is for DEDA class in 2017.