synopsys-vcs

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Here are 10 public repositories matching this topic...

tatan432 / AES_ENCODER

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RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.

digital rtl aes-128 synthesis aes-encryption digital-design verilog-project encription synopsys-vcs synopsys-dc ee4415

Updated Dec 11, 2020
Verilog

SimplHDL / simplhdl

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Simulation and implementation flow for hardware description languages

asic fpga simulation vhdl verilog vivado systemverilog implementation questasim quartus systemrdl cocotb synopsys-vcs

Updated Sep 3, 2026
Python

vb000 / vcs-slave-mode

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Example to control VCS simulation with a C/C++ program. This involves VCS output a shared object instead of an executable (simv).

verilog-simulator shared-object synopsys-vcs

Updated Mar 5, 2020
Makefile

cong2738 / May_team_project_I2C_SPI

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UVM based Verification of SPI_Protocol and I2C_Protoccol. A Serial intra System Communication Peripheral Protocol

c fpga i2c verilog spi vivado systemverilog uvm verdi microblaze axi hardware-description-language basys3-fpga synopsys-vcs

Updated Jul 24, 2025
VHDL

SeanS4 / rv32im-out-of-order-processor

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32-bit RISC-V processor implementing out-of-order execution, register renaming, and precise retirement in SystemVerilog.

rtl systemverilog computer-architecture risc-v microarchitecture verdi rv32im synopsys-vcs synopsys-dc out-of-order-execution register-renaming

Updated Aug 13, 2026
SystemVerilog

grandhisrivyshnavi-alt / SPI_Master_Core

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APB based SPI master protocol

digital linting verilog synthesis synopsys-vcs synopsys-dc

Updated Apr 13, 2026

pocper / IC_Contest

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全國大學校院積體電路設計競賽實作練習

verilog synopsys-vcs synopsys-dc cadence-innovus ic-contest

Updated Apr 25, 2026
Verilog

PremShah0208 / Fixed-Point-Matrix-Multiplication

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3x3 Q4.4 fixed-point matrix multiplier designed in Verilog and verified using Synopsys VCS and DVE.

rtl matrix-multiplication verilog fixed-point hardware-designs digital-design synopsys-vcs

Updated Aug 10, 2026
Verilog

Rakesh-2306 / Ultra-Lightweight-RISC-V-Architecture-for-Anomaly-Detection-in-Healthcare-Application

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Designed a lightweight 3-stage RISC-V processor for anomaly detection applications using Verilog, with RTL verification, synthesis, floorplanning, placement, CTS, routing, and STA using Synopsys VCS, Design Compiler, and ICC2.

routing tcl riscv verilog synthesis risc synopsys risc-v placement tcl-scripts verilog-project static-timing-analysis floorplanning verilog-code synopsys-vcs synopsys-dc synopsys-iccii clock-tree-synthesis

Updated Oct 21, 2025
Verilog

talsania / quartic-rtl2gds

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complete walkthrough of the vlsi design process for an equation Y = 4^X development to sta, using synopsys

synopsys synopsys-vcs synopsys-dc synopsys-iccii rtl-to-gdsii synopsys-primetime

Updated Apr 8, 2026
C

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