sar-adc

SAR ADC design knowledge base for agentic IC design: architecture, CDAC, comparator, bootstrap, async logic, integration, and Spectre verification. Includes taped-out 11-bit reference.

20bit SAR ADC 行为级建模与验证（Python），含 RTL 对照与冻结证据链

Designed a high-speed two-stage dynamic comparator for SAR ADCs using a StrongARM latch with dynamic biasing. Achieved 1.024 GHz speed, 90.26 ps delay, 5.23 µV noise, and 52.48 fJ energy, with a FoM of 2.18, proving suitability for high-speed ADCs.

Design and Simulation of Fully DIfferential 8-bit SAR ADC

Example describing the basic functionality of the ADC in tinyAVR 1-series.

Design, Simulation and FPGA Implementation of an 8-bit SAR ADC Controller using Verilog on Xilinx PYNQ-Z2 FPGA.

SAR ADC 数值验证与频谱分析（含残差查表与指标口径）

An introduction to adc's on megaavr 0 series

MTB code example

MTB code example

MTB code example

8-bit SAR ADC in SkyWater 130 nm: schematic to DRC/LVS-clean full-chip layout with open-source tools

SAR ADC 数字处理 RTL 与校准验证源码集

MTB code example

100KSPS 8-bitSuccessive Approximation Register (SAR) analog-to-digital converter (ADC) for Low-power Applications (UNIC-CASS program by IEEE CASS)

MTB code example

MTB code example

Cooperated by Chen Xuanren, Yuan Yiming, Zhang Changxiang and Zhu Yanxiang.

MTB code example

12bit 校准 SAR ADC 行为级建模（Python + Verilog-A + 可综合 RTL）