opentitan

Generic TL-UL to APB protocol adapter. Connects any APB peripheral to a TileLink Uncached Lightweight (TL-UL) crossbar for Ibex/OpenTitan RISC-V SoCs.

Keccak Message Authentication Code (KMAC) and Secure Hashing Algorithm 3 (SHA3)

The mailbox IP block in the OpenTitan Integrated design implements a request-response channel that the host System-on-Chip (SoC) may use to request security ser

OpenTitan UART IP - Full duplex serial communication peripheral with programmable baud rate, RX/TX buffers, and interrupt support

OpenTitan Rv Core Ibex IP block

Analog to Digital Converter Control Interface

ROM controller (rom_ctrl) is the connection between the chip and its ROM

This document specifies the OTP MACRO hardware IP functionality.

System Reset Controller (sysrst_ctrl) that provides programmable hardware-level responses to trusted IOs and basic board-level reset sequencing capabilities

Cryptographically Secure Random Number Generator (CSRNG)

OpenTitan Flash Ctrl IP block

Entropy Distribution Network (EDN) interfaces to the CSRNG IP module

Debugging in RISC-V can be done using one of the following mechanisms:

OpenTitan Prim Xilinx IP block

RISC-V Debug System wrapper functionality

Entropy Source: interface to an external physical random noise generator

I2C controller

OpenTitan Prim Generic IP block

SRAM memory controller

RISC-V timer module provides a configurable number of 64-bit counters