digitaldesign

EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!

Very simple Cortex-M1 SoC design based on ARM DesignStart

5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.

This repository contains scripts that I create through my digital design course in Verilog, VHDL, SystemVerilog etc..

RTL Design and Synthesis Workshop using Verilog with Sky130 Technology

VHDL tutorial

FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.

This repository contains different modules which execute arithmetic operations.

Verilog Code Challenge – KVLSI Kohort 2

VHDL controller for dynamic protocol switching (CAN, LIN, FlexRay).

Full AES (Verilog)

UVM-based memory verification project implemented using SystemVerilog, demonstrating read/write verification, assertions, scoreboard design, TLM analysis ports, and UVM best practices. Developed incrementally for learning, practice, and portfolio showcase in design verification.

8-input pipelined adder tree in Verilog with simulation & synthesis results.

A repo to store the coursework I do in college! 🎓

AMBA AHB Protocol implementation in Verilog with Single Master and Four Slaves including Decoder, Multiplexer, FSM based Master, Memory Mapped Slaves and Testbench Verification.

CipherX is a verification project for Advanced Encryption Standard (AES-128) using Universal Verification Methodology (UVM). It leverages Verilog, SystemVerilog, and Python to ensure robust encryption algorithm validation, integrating comprehensive UVM components and tests.

Parameterized and pipelined SystemVerilog implementation of a Bitonic Sorting Network.

A car parking slot management system implemented using FPGA for efficient vehicle detection and slot allocation. Utilizes hardware-based logic for real-time monitoring and automation.

RTL Designs along with testbenches to verify them written in Verilog. Icarus Verilog an open source simulator was used for simulations.

End-to-end RTL to GDSII ASIC physical design implementation at 28nm using Synopsys DC and ICC2 with full timing closure and DRC clean signoff.