chipforge

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TatsuProject / ChipForge_SN108

ChipForge (SN108) introduces the first digital design subnet for decentralized hardware innovation. This subnet enables miners to compete in designing real silicon. Processor development is organized into on-chain challenges — spanning AI accelerators, cryptographic modules, mini-GPUs, and other critical components.

subnet hardware-designs tatsu bittensor ai-accelerator chipforge bittensor-subnet sn108

Updated Sep 25, 2026
Python

TatsuProject / chipforge-mcu

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Open-source RISC-V processor core with hardware cryptography acceleration, developed through decentralized hardware competitions on Bittensor Subnet 84 (ChipForge).

cryptography open-hardware riscv systemverilog verilator hardware-verification cpu-design hardware-design riscv-crypto mircocontroller chip-design bittensor riscv-core chipforge bittensor-subnet scalar-crypto

Updated Apr 25, 2026
SystemVerilog

TatsuProject / chipforge_eda_server

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EDA server for simulating and validating hardware designs described in Verilog/SystemVerilog, focusing on functionality, performance, area, and power evaluation.

eda verilog systemverilog verilator bittensor chipforge

Updated Sep 24, 2026
Python

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