cache-controller

Two Level Cache Controller implementation in Verilog HDL

2-way set-associative cache controller in Verilog with single-port SRAM interface.

Direct-Mapped L1 Cache Controller with Tag Matching, Hit/Miss FSM, and Write-Back / Write-Allocate Policy.

32-bit Direct Mapped Cache Controller implemented in Verilog HDL using Xilinx Vivado.

Modular direct-mapped cache controller in Verilog featuring, write-back and write-allocate policies, FSM-based control, dirty block eviction, and self-checking verification

A cache controller implementation in VHDL for the demonstration of SRAM and SDRAM.

A parameterized Verilog implementation of a Direct-Mapped Write-Back Write-Allocate Cache Controller with configurable memory latency.

A cache controller managing a 4-way set-associative cache memory with PLRUt cache replacement and a main memory

32KB 4-Way Set-Associative L1 Cache Controller with Non-Blocking MSHR, Tree-PLRU, and AXI4 Refills targeting SkyWater 130nm.

Verilog-based cache controller implementing hit/miss detection, tag management, and FSM-based memory control.

Phase-2 Cycle-2: Memory & Architecture Foundations

RTL implementation and class-based verification of a Direct-Mapped Cache Controller using SystemVerilog with a self-checking scoreboard, directed and constrained-random testing.

Two-Level Cache Controller using Verilog HDL with L1 Direct Mapped Cache, L2 4-Way Set Associative Cache, LRU Replacement and Write-Back Policy.

cache controller verification

Fault-tolerant RTL cache controller with fault injection and recovery FSM

COE758 - This course covers advanced computing systems with emphasis on system architecture, memory hierarchy (Cache, Virtual memory), processor-peripheral interfacing, and bus organization. Laboratory projects include Cache Controller and VGA display design using FPGA. This course is taken at TMU, formally known as Ryerson.