acp_7_x: clear DMA IO stutter and PWA defaults to fix I2S loopback noise - #11176
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ACP DMA linked-list, IO stutter, and PWA control registers retain power-on defaults that can affect I2S DMA transfers: - ACP_DMA_CH_LINKED_LIST_EN: DMAChIOStutEn (bits 24:15) defaults to all 1s - ACP_DMA_IO_STUT_TIMER_LIMIT: IO stutter timer defaults are non-zero - ACP_DMA_CH_PWA_CTRL: PWA DMA control defaults are enabled Clear these registers during platform init, before DMA channel setup, to disable DMA IO stutter and PWA features that cause I2S loopback noise. Signed-off-by: sneha-voona <sneha.voona@amd.com>
sneha-voona
requested review from
bhiregoudar and
sunilkumardommati
as code owners
September 8, 2026 10:31
bhiregoudar
approved these changes
Sep 8, 2026
PR 11176: test resultsRun date: 2026-09-08 11:26 UTC Tested commit: ec0228f1bd89f725ce23a27c494659af4ad183fa
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kv2019i
approved these changes
Sep 8, 2026
Collaborator
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Fuzzer fails are known , tracked in #11157 . Rest looks good, proceeding with merge. |
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ACP DMA linked-list, IO stutter, and PWA control registers retain power-on defaults that can affect I2S DMA transfers:
Clear these registers during platform init, before DMA channel setup, to disable DMA IO stutter and PWA features that cause I2S loopback noise.