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sakshigalle/README.md

𝓗𝓲, π“˜'𝓢 𝓒π“ͺ𝓴𝓼𝓱𝓲

RTL Design β€’ Verilog HDL β€’ ASIC Design β€’ Semiconductor Technology

About Me

Electronics & Communication Engineering Student

Interested in:

  • Digital VLSI
  • RTL Design
  • ASIC Design Flow
  • Semiconductor Technology

Tech Stack

Verilog SystemVerilog Cadence Synopsys Git Linux

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  1. UART-Verilog UART-Verilog Public

    UART (Universal Asynchronous Receiver Transmitter) implemented in Verilog HDL.

    Verilog

  2. Digital-VLSI-Portfolio Digital-VLSI-Portfolio Public

    A collection of Digital VLSI, RTL Design, Verilog HDL, and semiconductor design projects with simulations, documentation, and learning notes.

    Verilog

  3. VLSI VLSI Public

    Forked from SubZer0811/VLSI

    All the projects and assignments done as part of VLSI course.

    Verilog