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1. huawei-csl/rtlscout huawei-csl/rtlscout Public

   RTLScout is a agentic RTL optimization framework

   Verilog 48 9

2. huawei-csl/spire-hdl huawei-csl/spire-hdl Public

   Spire is a Python embedded domain-specific language (DSL) for RTL generation. Its built-in optimizations reduce area and delay of circuits and often beat the traditional Verilog/Yosys flow.

   Python 38 5

3. ioda_lidar ioda_lidar Public

   Open source time-of-flight 3D lidar from scratch: Optics, PCB, FPGA incl TDC, FW, SW, UI.

   10

4. tdc_kernel_driver tdc_kernel_driver Public

   Time-to-digital linux kernel driver and peripheral, tested on FPGA RISC-V platform

   C 1

5. SpinalDev SpinalDev Public

   Docker Development Environment for SpinalHDL

   Dockerfile 20 2

6. aig-opt aig-opt Public

   Pure Python AIG (And-Inverter Graph) optimizer with FRAIG sweeping, NPN-guided DAG-aware rewriting, resubstitution, and stochastic multi-restart optimization. Benchmarks against Yosys and ABC.

   Python