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1. QPulse-Tiny-ECG-classifier-ASIC QPulse-Tiny-ECG-classifier-ASIC Public

   My AUC Silicon Sprint Project a tiny 1D-CNN accelerator generated via the HLS4ML Library, taped out in Sky Water 130nm using LibreLane

   Verilog

2. Elastic-Buffer-Design-UVM-Verification Elastic-Buffer-Design-UVM-Verification Public

   An Elastic Buffer Design and a UVM Verification environment for verifying USB 3 Gen 1 EB

   SystemVerilog 2

3. pyuvm-asyncio-HIL pyuvm-asyncio-HIL Public

   Forked from pyuvm/pyuvm

   PyUVM decoupled from cocotb, patched with asyncio to be used for Hardware-In-Loop HIL testing

   Python

4. Accelerator-HW-TB Accelerator-HW-TB Public

   Tcl

5. MIPI-D-PHY-TX-RX MIPI-D-PHY-TX-RX Public

   Implementation of the MIPI D-PHY IP on FPGA

   SystemVerilog 2

6. petalinux-demo petalinux-demo Public

   A Demo showcasing the integration of custom HW IP + Xilinx IPs & a petalinux generated distro

   C