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ecad: HDI - back-side placement, microvias, via-in-pad, pinned copper - #927
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…way KiCad flips PcbLayer::flipped; kicad_board::flip_to_back mirrors local y, negates pad angles and swaps front/back layers on the IR the router sees; the writer emits the library body the same way (layers, coordinates, mirrored text) so KiCad loads it with no lib_footprint_mismatch. A mixed-side test board routes with 0 DRC violations. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
- loon: [EcadVia ...], [EcadViaSpan x y d drill net from to] and [EcadTrace ...] lay copper by hand, pinned (CopperSource::Manual). - route --microvia D,DRILL: outer-to-adjacent spans are microvias; the maze clears them at that size and the CLI writes them at it; KiCad gets them as (via micro). - via-in-pad: a pinned via inside a same-net pad makes the pad reachable on the via's layers, so a BGA ball leaves on the inner layer instead of the router drilling between balls. - the second pass and leaf trimming never rip hand-laid copper. A 0.5 mm BGA-153 with a microvia in each signal ball: 10/11 nets out (was 7/11 with through vias only). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…the board brings its own fanout, one-dielectric via hops, raster-prefiltered via sites, cached pin fields The brain board's first pass: 619 connections in 195 s (it did not finish in 2 hours before). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
The brain board (619 connections, 0.4 mm BGA, 8-layer HDI): 2:09 at 73% routed, against >30 min (timed out) for the full arsenal at 74%. - --fast: no rip-up, negotiation, joint repair, CLI second pass, direct links or plane-stitch repair; legalization keeps only via merge and dead-copper pruning; a failed speculative search is not re-run sequentially. - drc::net_islands: island counts for many nets from one connectivity build; the CLI used to rebuild the whole board's connectivity per net. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…zone per candidate via), stderr progress with elapsed time per phase and per net Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…OINT is set); spans over the route phases, router passes, repairs per net, zone fill and connectivity Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
… net-scoped continuity (only the net's copper, pours still filled against the board); batch island count in the second pass Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…ane stitching) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…second pass is one greedy round (no negotiation / rip-up / joint repair) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
… per pad pair / pad), skip plane nets in direct links, check the budget inside a net Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
… an FNV hash of the canonical input + options); VCAD_ROUTE_REDO=first|second, VCAD_ROUTE_CHECKPOINT=0 Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…(drc::stranded_pads); VCAD_ROUTE_SKIP=links,stitch to measure each repair Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…hem all (an HDI stack F-In1-In3 was emitted as an F-In1 via under an In3 route); dedupe and leaf-trim treat a via's span as part of its identity and a stacked partner as a live end. brain fast route 490 -> 316 unconnected Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
… to pin before the full route Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…e vias crossing that layer as obstacles, grouped by the side each net leaves toward), vcad route --escape LAYERS; ratsnest keeps air-wires between pads not yet joined by copper instead of skipping every net that has a trace; escape channel width counts both sides of a gap Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
… the connectivity layer stack - In7/In8 copper had an empty layer mask) Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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What the rose brain board (RK3588S2, 0.4 mm FCCSP1253) needs from vcad.
[EcadPlaceBack ref x y rot]. KiCad's flip: front/back layers swap, local y mirrors, pad angles negate. It runs on both the IR the router sees and the library body the writer emits. A mixed-side test board routes with 0 KiCad DRC violations, including nolib_footprint_mismatch.[EcadVia],[EcadViaSpan x y d drill net from to]and[EcadTrace]are now converted. Before this, the types existed but convert ignored them. They are pinned asCopperSource::Manual, and the second routing pass and leaf trimming never rip them.vcad route --microvia D,DRILLtreats outer-to-adjacent spans as microvias. The maze clears each via at its span's size, the CLI writes them at that size, and the writer emits(via micro …).Test: a 0.5 mm BGA-153 with a microvia in each signal ball gets 10 of 11 nets out, against 7 of 11 with through vias only.
Since then (brain board work)
--fast; stderr progress per phase; OpenTelemetry traces (OTEL_EXPORTER_OTLP_ENDPOINT); per-phase checkpoints (<out>.ckpt/,VCAD_ROUTE_REDO,VCAD_ROUTE_CHECKPOINT=0)EcadBoard 10, In7/In8 in the stackup and in the connectivity layer stack--only NET,--escape LAYERS(multi-layer BGA escape planner, off by default — not a win yet),VCAD_ROUTE_SKIP=links,stitch🤖 Generated with Claude Code