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8bit-ALU-vhdl
8bit-ALU-vhdl PublicThe project involves designing an 8-bit Arithmetic Logic Unit (ALU) using VHDL. The ALU performs eight different operations based on a 3-bit opcode, making it a fundamental component in digital cir…
VHDL 1
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parametric-low-power-alu-verilog
parametric-low-power-alu-verilog PublicA configurable Arithmetic Logic Unit (ALU) supporting 12 operations with parameterized data width. Designed with low-power techniques including clock gating and operand isolation. Simulated using X…
Verilog 1
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visual-search-dl-faiss
visual-search-dl-faiss PublicA content-based image retrieval prototype that uses a custom-trained Convolutional Neural Network (CNN) on CIFAR-10 and a FAISS vector database to compute and retrieve image embeddings. Built with …
Jupyter Notebook 1
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wallace_tree_multiplier
wallace_tree_multiplier PublicStructural RTL implementation of an 8-bit Wallace Tree Multiplier with clock gating and pipelining, designed using compressor-based logic for area-efficient, high-speed multiplication. Synthesizabl…
Verilog 1
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autosentry
autosentry PublicAutoSentry is a decentralized, blockchain-powered AI agent that autonomously monitors IoT sensor data, detects anomalies using a lightweight machine learning model, and triggers on-chain actions.
Python
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iris_classification_sagemaker
iris_classification_sagemaker PublicThe project implements a complete machine learning pipeline to classify iris flower species using the classic Iris dataset. The workflow is built and tested on Amazon SageMaker Studio Lab, simulati…
Jupyter Notebook
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