Undergraduate at Nanjing University (VLSI Design & System Integration), graduating in 2027.
I work on AI accelerator architecture, RISC-V systems, and hardware-software co-design — connecting workload mapping and communication-aware scheduling with RTL implementation and reproducible verification.
Personal website · Vulcan portfolio · Public RTL Showcase
- Nanjing University — VLSI Design & System Integration
- Campus locations: Nanjing (Year 1); Suzhou (Years 2–4)
- Expected graduation: 2027
| Period | Experience |
|---|---|
| Sep–Dec 2026 | Microsoft Research Asia (MSRA) — Research Intern, Systems Research Group, Beijing. Group website ↗ |
| Jan–May 2027 | Nanyang Technological University (NTU), Singapore — Selected for an upcoming government-sponsored undergraduate exchange. Program website ↗ |
Methods: DNN mapping, inter-layer scheduling, NoC and memory-system data movement. I contribute to HyperCut and maintain a Crane reproduction lab.
With Argus AI Team, I contribute to Argus / Microsoft · original project, a persistent multi-agent runtime, its chip-design vertical, interfaces and evidence-driven evaluation.
Vulcan is my independent AI-native hardware engineering project, not part of Argus AI Team. It connects scoped RTL implementation, verification, independent review and reproducible delivery across eight hardware families, with SABLE and ten component IPs as supplementary projects. Functional simulation, static timing and design-specific board execution are reported separately.
| Family | Focus and public evidence |
|---|---|
| ACE-2 / ACE-3 MP | W4A8 persistent RTL dialogue and native AWQ W4A16 research. ACE-2 has accepted two-turn, four-token-per-turn simulation with 24 retained K/V layers and zero mismatches. ACE-3 has verified G128 projection and bounded FP16-boundary blocks; full-regression, full-model and hardware acceptance remain open. |
| ANVIL — Q / E | Embeddings and quantized inference. Original E1–E3/Q1 retain bounded workload HIL; Q1 executes Q16.16 after binary16 storage conversion. QN1/EN1 now integrate native-model tops with numerical/smoke or contract checks, not end-to-end model acceptance. D1 has functional/STA records; D2 has initial numerical receipts. |
| HAMMER-V | Five-stage RV64IM/RV64IMA research through privilege, caches and Sv39. V4 reaches Linux 6.6.1 minimal user-space /init in Verilator RTL simulation; V5 integrates core/SoC/top with scoped behavioral/synthesis checks. The V4 run ends in a PID 1 exit panic, not an interactive shell or FPGA Linux boot. |
ACE organization mirrors: ACE-2 · ACE-3.
Generations stay within their families rather than being counted as fabricated chips:
| Family | Product lines |
|---|---|
| RIVET | A — AES/GCM · H — hashing and NTT/ML-DSA; H4/H5 publish RTL, tests and reports, without raw public STA/board receipts. |
| BILLET | T — FFT/IFFT · F — filtering and audio; F5 adds eight-microphone beamforming/NLMS RTL, without measured acoustic hardware-performance claims. |
| SWAGE-S | Imaging through bounded programmable detection; S4/S5 publish functional and positive 100 MHz post-fit timing records, not pretrained-model accuracy or board image-workload acceptance. |
| BELLOWS — L / N | Codec and networking RTL through L5/N5, including bounded Zstandard and custom MoE dispatch. L4 has positive STA; L5 synthesis timed out and N4/N5 retain hold violations. |
| CRUCIBLE-G | Rasterization through bounded LBVH/ray queries and SVGF; G4/G5 have functional and positive 100 MHz STA records, not hardware-rendered FPS measurements. |
| FURNACE-X | Heterogeneous integration through X4, including CPU/MMIO behavioral checks. Shared telemetry is not per-SoC board or Linux acceptance. The old networking line moved to BELLOWS-N and is not counted twice. |
Evidence snapshot: November 3, 2026, 22:52 UTC+8. Q4, N4/N5 and X3 retain negative hold slack despite passed labels. Shared SoftReg vector/telemetry records do not bind every named design to its own bitstream or CPU boot trace. See the portfolio's source and evidence notes and the pinned V4 Linux log; publication is not blanket hardware signoff.
SABLE explores four-stream reliable message transport. Vulcan Showcase indexes public engineering packages and ten reusable SystemVerilog IPs, not a count of physically verified chips.
64-Point FFT: folded streaming SDF, Q1.15, XSim/Python co-verification and routed Virtex-7 results. Two-Stage CMOS Op-Amp: TSMC 0.18 μm Miller compensation with Spectre AC/DC/transient verification.
- HyperCut: Fast Inter-Layer Scheduling via Directed Hypergraph and Early Filtering
https://arxiv.org/abs/2608.19296— Early filtering and hypergraph-based inter-layer scheduling for tiled DNN accelerators. - Argus: A General-Purpose Agentic Reasoning Runtime for Long-Horizon Tasks
https://arxiv.org/abs/2608.05144— A persistent, self-evolving runtime for long-horizon agentic reasoning.
- Personal website
https://ahappend.github.io/ - arXiv Author Profile
https://arxiv.org/a/0009-0002-5674-7448.html - ORCID
https://orcid.org/0009-0002-5674-7448 - X
https://x.com/hapouterwall - Instagram
https://instagram.com/hapouterwall - YouTube
https://www.youtube.com/@hapouterwall - Linktree
https://linktr.ee/sufeng_guo
Python C / basic C++ TypeScript SystemVerilog Verilog React Linux
- Nanjing University email
sufeng_guo@smail.nju.edu.cn - Gmail
hapouterwall@gmail.com - QQ Mail
sufeng_guo@qq.com