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8 changes: 8 additions & 0 deletions .github/workflows/ports.yml
Original file line number Diff line number Diff line change
Expand Up @@ -75,6 +75,10 @@ jobs:
run: zig build test
working-directory: port/wch/ch32v

- name: wch/ch32h
run: zig build test
working-directory: port/wch/ch32h

build:
name: "Build"
runs-on: ${{ matrix.os }}
Expand Down Expand Up @@ -143,6 +147,10 @@ jobs:
run: zig build -Doptimize=ReleaseSmall
working-directory: examples/wch/ch32v

- name: wch/ch32h
run: zig build -Doptimize=ReleaseSmall
working-directory: examples/wch/ch32h

- name: no_hal/stm32_l031
run: zig build -Doptimize=ReleaseSmall
working-directory: examples/no_hal/stm32_l031
Expand Down
2 changes: 2 additions & 0 deletions build.zig
Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,7 @@ const port_list: []const struct {
.{ .name = "rp2xxx", .dep_name = "port/raspberrypi/rp2xxx" },
.{ .name = "stm32", .dep_name = "port/stmicro/stm32" },
.{ .name = "ch32v", .dep_name = "port/wch/ch32v" },
.{ .name = "ch32h", .dep_name = "port/wch/ch32h" },
.{ .name = "msp430", .dep_name = "port/texasinstruments/msp430" },
.{ .name = "mspm0", .dep_name = "port/texasinstruments/mspm0" },
.{ .name = "tm4c", .dep_name = "port/texasinstruments/tm4c" },
Expand Down Expand Up @@ -70,6 +71,7 @@ pub const PortSelect = struct {
rp2xxx: bool = false,
stm32: bool = false,
ch32v: bool = false,
ch32h: bool = false,
msp430: bool = false,
mspm0: bool = false,
tm4c: bool = false,
Expand Down
1 change: 1 addition & 0 deletions build.zig.zon
Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,7 @@
.@"port/texasinstruments/mspm0" = .{ .path = "port/texasinstruments/mspm0", .lazy = true },
.@"port/texasinstruments/tm4c" = .{ .path = "port/texasinstruments/tm4c", .lazy = true },
.@"port/wch/ch32v" = .{ .path = "port/wch/ch32v", .lazy = true },
.@"port/wch/ch32h" = .{ .path = "port/wch/ch32h", .lazy = true },

.@"modules/riscv32-common" = .{ .path = "modules/riscv32-common" },
.@"modules/rtt" = .{ .path = "modules/rtt" },
Expand Down
43 changes: 43 additions & 0 deletions examples/wch/ch32h/build.zig
Original file line number Diff line number Diff line change
@@ -0,0 +1,43 @@
const std = @import("std");
const microzig = @import("microzig");

const MicroBuild = microzig.MicroBuild(.{
.ch32h = true,
});

fn add_example(b: *std.Build, mb: anytype, comptime name: []const u8, optimize: std.builtin.OptimizeMode) void {
const v3f = mb.add_firmware(.{
.name = "v3f",
.root_source_file = b.path("src/ch32h417_only/" ++ name ++ "_v3f.zig"),
.optimize = optimize,
.target = mb.ports.ch32h.chips.ch32h417_v3f,
});

const v5f = mb.add_firmware(.{
.name = "v5f",
.root_source_file = b.path("src/ch32h417_only/" ++ name ++ "_v5f.zig"),
.optimize = optimize,
.target = mb.ports.ch32h.chips.ch32h417_v5f,
});

const merged_bin = mb.ports.ch32h.merge(b, v3f.get_emitted_elf(), v5f.get_emitted_elf(), name ++ "_merged.bin");

const install = b.addInstallFileWithDir(merged_bin, .{ .custom = "firmware" }, name ++ ".bin");
b.getInstallStep().dependOn(&install.step);
}

const examples = [_][]const u8{
"blinky",
"interrupts",
};

pub fn build(b: *std.Build) void {
const optimize = b.standardOptimizeOption(.{});

const mz_dep = b.dependency("microzig", .{});
const mb = MicroBuild.init(b, mz_dep) orelse return;

inline for (examples) |example| {
add_example(b, mb, example, optimize);
}
}
14 changes: 14 additions & 0 deletions examples/wch/ch32h/build.zig.zon
Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
.{
.name = .examples_wch_ch32h,
.fingerprint = 0x98c6b66930eca2b,
.version = "0.0.0",
.dependencies = .{
.microzig = .{ .path = "../../.." },
},

.paths = .{
"build.zig",
"build.zig.zon",
"src",
},
}
41 changes: 41 additions & 0 deletions examples/wch/ch32h/src/ch32h417_only/blinky_v3f.zig
Original file line number Diff line number Diff line change
@@ -0,0 +1,41 @@
const microzig = @import("microzig");

pub const panic = microzig.panic;

pub const std_options = microzig.std_options(.{});

comptime {
_ = microzig.export_startup();
}

const clocks = microzig.hal.clocks;
const gpio = microzig.hal.gpio;

const PFIC = microzig.chip.peripherals.PFIC;

fn delay(cycles: u32) void {
for (0..cycles) |_| {
asm volatile ("nop");
}
}

pub fn main() !void {
clocks.init();
clocks.enable_gpio(.c);

const pc2: gpio.Pin = .{ .port = .c, .number = 2 };
pc2.apply(.{
.mode = .{ .output = .general_purpose_open_drain },
.speed = .max_50MHz,
.pull = .disabled,
});

// Wakeup V5F
PFIC.WAKEIP1.raw = 0x10000 & ~@as(u32, 0x3FF);
PFIC.SCTLR.raw |= (1 << 5);

while (true) {
pc2.toggle();
delay(20_000_000);
}
}
31 changes: 31 additions & 0 deletions examples/wch/ch32h/src/ch32h417_only/blinky_v5f.zig
Original file line number Diff line number Diff line change
@@ -0,0 +1,31 @@
const microzig = @import("microzig");

pub const panic = microzig.panic;

pub const std_options = microzig.std_options(.{});

comptime {
_ = microzig.export_startup();
}

const gpio = microzig.hal.gpio;

fn delay(cycles: u32) void {
for (0..cycles) |_| {
asm volatile ("nop");
}
}

pub fn main() !void {
const pc3: gpio.Pin = .{ .port = .c, .number = 3 };
pc3.apply(.{
.mode = .{ .output = .general_purpose_open_drain },
.speed = .max_50MHz,
.pull = .disabled,
});

while (true) {
pc3.toggle();
delay(120_000_000);
}
}
58 changes: 58 additions & 0 deletions examples/wch/ch32h/src/ch32h417_only/interrupts_v3f.zig
Original file line number Diff line number Diff line change
@@ -0,0 +1,58 @@
const microzig = @import("microzig");

pub const panic = microzig.panic;

pub const std_options = microzig.std_options(.{});

comptime {
_ = microzig.export_startup();
}

const cpu = microzig.cpu;
const clocks = microzig.hal.clocks;
const gpio = microzig.hal.gpio;

const PFIC = microzig.chip.peripherals.PFIC;

pub const microzig_options: microzig.Options = .{
.interrupts = .{ .SW = sw_handler },
};

const pc2: gpio.Pin = .{ .port = .c, .number = 2 };

fn sw_handler() callconv(cpu.riscv_calling_convention) void {
cpu.interrupt.clear_pending(.SW);

pc2.toggle();
}

fn delay(cycles: u32) void {
for (0..cycles) |_| {
asm volatile ("nop");
}
}

pub fn main() !void {
clocks.init();
clocks.enable_gpio(.c);

pc2.apply(.{
.mode = .{ .output = .general_purpose_open_drain },
.speed = .max_50MHz,
.pull = .disabled,
});

cpu.interrupt.enable(.SW);

if (cpu.interrupt.current_core() != .v3f)
@panic("unexpected current core");

// Wakeup V5F
PFIC.WAKEIP1.raw = 0x10000 & ~@as(u32, 0x3FF);
PFIC.SCTLR.raw |= (1 << 5);

while (true) {
cpu.interrupt.set_pending(.SW);
delay(20_000_000);
}
}
35 changes: 35 additions & 0 deletions examples/wch/ch32h/src/ch32h417_only/interrupts_v5f.zig
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
const microzig = @import("microzig");

pub const panic = microzig.panic;

pub const std_options = microzig.std_options(.{});

comptime {
_ = microzig.export_startup();
}

const cpu = microzig.cpu;
const gpio = microzig.hal.gpio;

fn delay(cycles: u32) void {
for (0..cycles) |_| {
asm volatile ("nop");
}
}

pub fn main() !void {
if (cpu.interrupt.current_core() != .v5f)
@panic("unexpected current core");

const pc3 = gpio.Pin{ .port = .c, .number = 3 };
pc3.apply(.{
.mode = .{ .output = .general_purpose_open_drain },
.speed = .max_50MHz,
.pull = .disabled,
});

while (true) {
pc3.toggle();
delay(120_000_000);
}
}
3 changes: 3 additions & 0 deletions port/wch/ch32h/README.md
Original file line number Diff line number Diff line change
@@ -0,0 +1,3 @@
# WCH CH32H417 Package

SVD file extracted from `MounRiver_Studio_Community_Linux_x64_V190.zip`.
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