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Harden UART/DMA recovery and embedded input processing - #21

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ramseymcgrath merged 1 commit into
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codex/embedded-reliability
Oct 30, 2026
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ramseymcgrath merged 1 commit into
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codex/embedded-reliability

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UART responses could be truncated or interleaved, DMA receive laps could appear empty, and synchronous display work could stall input processing. This change queues complete response records, detects DMA RX loss before delivering data, and advances the default TFT refresh through cooperative row DMA.

Changes:

  • Route command replies through a shared UART queue while keeping debug stdio off the protocol UART; preserve startup polling and IRQ-to-DMA handoff.
  • Track RP2350 self-trigger DMA progress, validate snapshots and copies, reset partial parsers, and release injected controls on receive loss.
  • Standardize bridge control packets, fix reply markers and click masks, and preserve physical button holds when synthetic buttons release.
  • Fix timer rollover, Core 1 wake-ups and queue ordering, parser bounds, spinlock ownership, TFT register accesses, and LED DMA behavior.

Validation: all eight host regression suites pass with address and undefined-behavior sanitizers, including concurrent queue producers, timer/count rollover, DMA overwrite during copying, fragmented replies, and framebuffer ownership. git diff --check passes. Firmware compilation and on-board validation remain outstanding because the Pico SDK and ARM build tools are unavailable locally.

Compatibility and limits:

  • Flash bridge and proxy from the same revision; control opcodes are documented in README.
  • After RX loss, the sender must provide a packet-boundary idle gap of at least 1 ms. Traffic is discarded during recovery; ambiguous long sampling pauses produce lower-bound discard counts.
  • The optional TFT_HW_ACCEL path and explicit splash/error refreshes remain synchronous.

@ramseymcgrath
ramseymcgrath merged commit 6901d6f into master Oct 30, 2026
7 of 8 checks passed
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