Wishbone B4 bindings for the neutral register contract.
Part of the Tape-Out IP library: Bluespec IP over the
bus-neutral contracts in hwcore, assembled by
xirang. Maturity runs planned -> simulated ->
fpga-proven -> asic-ready -> silicon-proven.
Simulated. Two binders attach an IP that only speaks the bus-neutral contract to Wishbone B4 slave pins in pipelined mode:
| Binder | Target | Behaviour |
|---|---|---|
mkWbBind |
RegIf, answers at once |
STALL_O is always low; a transfer starts when CYC_I and STB_I are high, and ACK_O or ERR_O follows in the next cycle |
mkWbBindT |
RegTarget, may stall |
STALL_O is high while a transfer is outstanding, so the master holds the next one |
Both follow the pipelined rules of the specification: a transfer starts on CYC, STB and no STALL (RULE 3.57 and 3.58), acknowledgements come independently of STB (OBSERVATION 3.10), and DAT_O is valid with ACK_O (RULE 3.65). A target error answers with ERR_O instead of ACK_O.
The testbench drives a pipelined master that puts four transfers on the bus back to back without waiting for acknowledgements, against a zero-wait and a stalling target. It checks the order and number of answers, a write followed by a read, an address that always errors, byte strobes, and that STB without CYC starts nothing.
Standard (non-pipelined) masters, RTY_O and tag signals are not implemented.
The specifications this IP is implemented against, with their links, digests and the clause-by-clause comparison, are kept on the spec branch.
任选其一：
SPDX-License-Identifier: MIT OR Apache-2.0 OR MulanPSL-2.0
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