UART with a 16550-compatible register profile and a native profile.
Part of the Tape-Out IP library: Bluespec IP over the
bus-neutral contracts in hwcore, assembled by
xirang. Maturity runs planned -> simulated ->
fpga-proven -> asic-ready -> silicon-proven.
Simulated. Written in Bluespec against the spec
contracts, with the register file generated from regmap.yaml. Three FIFO depths
synthesise clean with no scheduling warnings; the area curve is measured at six depths
and four further depths confirm the prediction never comes in low.
| FIFO depth | 1 | 2 | 4 | 8 | 16 | 32 |
|---|---|---|---|---|---|---|
| Area, um2 | 1689 | 1898 | 2533 | 3376 | 5001 | 8063 |
目前使用UC Agent测试
picker export uart_mmio.v --rw 1 --sname uart_mmio --tdir output/ -c -w output/uart_mmio.fst
ucagent output/ uart_mmio -s -hm --tui --mcp-server-no-file-tools --no-embed-tools
verilator --lint-only -Wall --top-module uart_mmio uart_mmio.v
任选其一：
SPDX-License-Identifier: MIT OR Apache-2.0 OR MulanPSL-2.0
除非另行说明，你提交的贡献按上述三者同时授权，不附加其他条件。