General-purpose timer: several channels with capture and compare.
Part of the Tape-Out IP library: Bluespec IP over the
bus-neutral contracts in hwcore, assembled by
xirang. Maturity runs planned -> simulated ->
fpga-proven -> asic-ready -> silicon-proven.
Planned. What sits in this repository today is the retired picorv32-era Verilog, kept for provenance; the Bluespec rewrite has not landed yet.
这里开始使用RS标识可读，不可写，但是特殊位可设置
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