Issues

• Missing raw_dims parameter in Module.Reg Class

  PyHDI/veriloggen#66 · Filter by author RuxueJ opened on Oct 7, 2025

• Which standard does this package follow?

  PyHDI/veriloggen#65 · Filter by author BlingBlingKing opened on May 13, 2025

• Please add support for VerilogA

  PyHDI/veriloggen#64 · Filter by author mwolodzk opened on Apr 2, 2025

• License does not have year or author clause

  PyHDI/veriloggen#63 · Filter by author lemoncmd opened on Sep 16, 2024

• Jupyter notebook 'hello_led.ipynb'

  PyHDI/veriloggen#62 · Filter by author zehonyi21 opened on Aug 9, 2024
  1

• Java runtime error

  PyHDI/veriloggen#61 · Filter by author VPIgnite99 opened on Feb 21, 2024

• # The task call part in veriloggen library is not generated correctly

  PyHDI/veriloggen#60 · Filter by author Hikakkun opened on Jan 24, 2024

• read_verilog_module does not support instances with unconnected ports, will generate a TypeError.

  PyHDI/veriloggen#58 · Filter by author darcy-wu opened on Aug 12, 2023

• Slice in Wire with two dimension

  PyHDI/veriloggen#47 · Filter by author LucasBraganca opened on Mar 21, 2022
  1

• Creating a combinational sequence

  PyHDI/veriloggen#46 · Filter by author kiteloopdesign opened on Jun 14, 2021

• to_verilog("file.v") creates two empty lines at beginning of file

  PyHDI/veriloggen#44 · Filter by author kiteloopdesign opened on May 18, 2021

• Creating input with literal BW in the form of [n:0] instead of [n-1:0]

  PyHDI/veriloggen#43 · Filter by author kiteloopdesign opened on Apr 30, 2021

• stream.source with only size without data read

  PyHDI/veriloggen#39 · Filter by author shtaxxx opened on Jan 28, 2021

• Bug of stream.ReduceDiv for signed values

  PyHDI/veriloggen#38 · Filter by author shtaxxx opened on Jan 26, 2021

• Inserting user-defined simulation code for Verilator mode

  PyHDI/veriloggen#37 · Filter by author shtaxxx opened on Jan 25, 2021

• Infinite read size for stream.source

  PyHDI/veriloggen#36 · Filter by author shtaxxx opened on Jan 25, 2021

• Explicit latency constraint between two stream objects which accesses to external resources outside of the stream.

  PyHDI/veriloggen#32 · Filter by author shtaxxx opened on May 14, 2020
  1

• Supporting multiple outstanding DMA requests

  PyHDI/veriloggen#26 · Filter by author shtaxxx opened on Apr 16, 2019
  1

• Online tutorial on binder/jupyter

  PyHDI/veriloggen#24 · Filter by author shtaxxx opened on Mar 27, 2019

• Travis CI -> CircleCI?

  PyHDI/veriloggen#23 · Filter by author shtaxxx opened on Mar 27, 2019
  4

• How to use from_verilog function in veriloggen

  PyHDI/veriloggen#20 · Filter by author bhargav3333 opened on Feb 18, 2019
  1

• Better Documentation/Tutorials

  PyHDI/veriloggen#19 · Filter by author xd009642 opened on Jan 29, 2019
  6

• realtime monitoring of simulation output

  PyHDI/veriloggen#16 · Filter by author sgherbst opened on Nov 6, 2017
  1

• Untimed mode (no clock-level FSM) of Thread for simulation

  PyHDI/veriloggen#8 · Filter by author shtaxxx opened on Jul 9, 2015

• Python PLI support for simulation

  PyHDI/veriloggen#5 · Filter by author shtaxxx opened on Jul 9, 2015