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MicroGridX/README.md

Sreekar Mallela

RTL Design and Verification • FPGA/ASIC Design

👨‍💻 About Me

I am an ECE undergraduate at IIIT Una with strong interest in:

  • RTL Design
  • FPGA-Based Systems
  • Digital IC Design
  • Verilog/SystemVerilog
  • ASIC Design Flow
  • FSM Design
  • Timing Analysis
  • SoC Architecture

Currently focused on building a strong foundation in:

RTL to GDS Flow

🌐 Connect With Me

📊 GitHub Activity

📊 GitHub Stats

# ⚙️ Tech Stack

Hardware / VLSI

Verilog SystemVerilog FPGA RTL Design Digital Design FSM

Programming

C C++ Python

Tools

Git GitHub VSCode Linux

🚀 Current Focus

  • RTL Coding in Verilog
  • FSM-Based Design
  • FPGA Projects
  • Processor Design Basics
  • Synthesizable Verilog
  • ASIC Design Flow (RTL-GDSII)

⚡ “Designing hardware one clock cycle at a time.”

Pinned Loading

  1. MicroGridX MicroGridX Public

  2. HDL-Bits-Solutions HDL-Bits-Solutions Public

    Solutions to HDLBits hardware description language problems, implemented one by one in Verilog/SystemVerilog to build a strong foundation in digital logic design, RTL coding, and verification princ…

    Verilog 1