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IIITD_Resources
IIITD_Resources PublicA curated collection of study resources, previous year papers, notes, assignments, labs, and projects for IIIT Delhi students.
Jupyter Notebook 4
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P3b-cadence-45nm-MAC
P3b-cadence-45nm-MAC Public: Full RTL-to-GDSII flow of an 8×8 MAC on 45 nm Cadence Genus/Tempus/Innovus with a debugging case study
Verilog 1
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pd-learning-portfolio
pd-learning-portfolio PublicHands-on VLSI and ASIC Physical Design projects covering Linux, Bash, TCL, Verilog, synthesis, STA, and Synopsys EDA tools.
Verilog
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P4-timing-closure-45nm
P4-timing-closure-45nm PublicTiming closure case study of an 8×8 MAC on Nangate FreePDK45 — quantifies library selection tradeoff, identifies architectural closure at 158.5 MHz
Verilog
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P3a-synopsys-dc-65nm
P3a-synopsys-dc-65nm PublicSynopsys Design Compiler synthesis of an 8×8 MAC unit on STMicroelectronics 65 nm CORE65LPSVT — 424 cells, timing MET at 200 MHz with +1.58 ns positive slack
Verilog
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