DSP / C++ / FPGA / SDR Engineer
C++17 DSP • Communication systems • Fixed-point DSP • Zynq/AD936x • Verilog • MATLAB/Simulink
Candidate of Technical Sciences — a research degree broadly comparable to a PhD

LinkedIn · Engineering portfolio · Case studies · laymob@gmail.com

I help R&D teams turn DSP and communication algorithms into verified C++ implementations and FPGA/RTL systems. My work is evidence-driven: reference models, deterministic test vectors, fixed-point design, FPGA/SDR integration, measurements, and reproducible engineering reports.

• Zynq/AD936x QPSK: 5.6 million fabric-loopback bits with zero errors; reported BER upper bound below 5.34e-7.
• Two-board RF link: differential QPSK over a 915 MHz cabled link with whole-burst rotation failures eliminated and payload BER around 4e-4.
• LoRa/SX1262 → ZynqSDR (M9): 732/732 captured packets passed payload CRC across the 500-attempt and overnight hardware campaigns, with zero detection misses.
• LoRa FPGA PER (M11, SF7/BW125, CR 4/5): measured PER 10% threshold ≈ −7.8 dB SNR versus ≈ −8.2 dB for the known-timing model (method and results). The comparison is not an absolute receiver sensitivity rating.
• FPGA timing: a continuous PL sample-time counter was verified across 47 captures spanning 803.7 s.
• Traceable implementation flow: MATLAB/Simulink reference models → fixed-point design → generated/manual RTL → Zynq/AD936x → RF/IQ measurements.

• C++ DSP development — implementation and review of FIR, Goertzel, resampling and correlation algorithms; deterministic tests, CMake integration and benchmarks.
• DSP / FPGA R&D — reference models, fixed-point implementation, RTL verification, Zynq/AD936x integration and measurable acceptance criteria.
• MATLAB / Simulink → hardware — reference models, numerical design, test vectors, HDL-oriented architecture, generated RTL, and Zynq integration.
• Technical review and debugging — focused work on DSP, SDR, synchronization, RF/IQ measurement, FPGA implementation, and reproducibility problems.

For focused R&D, consulting, or technical review work, contact me via email or LinkedIn.

A reusable C++17 DSP library with FIR, Goertzel, GCC-PHAT and rational resampling, deterministic tests, optional AVX2 acceleration, CMake package export and documented benchmark methods. Start with the reviewer quick check.

An end-to-end SDR engineering course and evidence base built around Zynq-7020 + AD936x. It connects signal theory, DSP models, fixed-point design, Verilog/FPGA, RF integration, IQ capture, and measurement reporting.

The in-fabric QPSK modem is validated on two independent boards over a controlled RF path, with reproducible RTL tests, machine-readable results, timing/resource reports, and measurement documentation.

A LoRa PHY and ToA/TDoA positioning research platform with a traceable MATLAB → Simulink → generated Verilog → ZynqSDR path.

The implementation includes continuous-IQ acquisition, LoRa decoding, BER/PER evaluation, fractional ToA, fixed-point streaming processing, generated HDL, hardware packet reception and PL timestamp metadata. M9 hardware campaigns reached 732/732 CRC-valid captured packets with zero detection misses. M11 reports measured FPGA SF7/BW125 PER curves for CR 4/5–4/8; the CR 4/5 PER 10% threshold is ≈ −7.8 dB SNR, compared with ≈ −8.2 dB in the known-timing model.

The next research milestones are controlled delay calibration, inter-receiver synchronization and synchronized multi-receiver TDoA; the repository does not yet claim calibrated hardware positioning.