CI: full validation matrix with sanitizers and native-ARM benchmarking - #2
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Six GitHub Actions jobs: Linux gcc, Linux clang, native arm64 (real ARM silicon via GitHub's free arm64 runners - the job also runs the clustered benchmark and uploads it, so ARM performance numbers are measured on hardware, not emulated), Windows MinGW-w64 (MSYS2/UCRT64), ASan+UBSan across all five suites, and ThreadSanitizer on the concurrency suite (with the mmap_rnd_bits=28 sysctl the TSan runtime needs on modern kernels). Debug and -DNDEBUG configurations everywhere. Local pre-flight: ASan+UBSan pass all five suites with zero findings. TSan is environmentally blocked under WSL2 (its injected interop mappings trip "unexpected memory mapping" at startup regardless of ASLR settings), so CI is the TSan executor of record. Test shims: the allocation counters in test_hnsw_graph.cpp and test_integration.cpp are now std::atomic - worker threads allocate their contexts during concurrent-build tests, and the plain size_t increment was a genuine (harness-side) data race TSan would have flagged. README gains the CI badge. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017ULiWeodALX2ZQiLKvTw25
The arm64 CI job ran the clustered benchmark on native ARM hardware: 0.995 float-exact recall@10 at 166 us/query (~6,000 QPS single thread), 4-thread 100k build in 9.5 s, reclaim 1.8 ms, graph load 0.018 s - with every recall figure bit-identical to x86-64. The "ARM performance pending real silicon" limitation is removed from the roadmap; CI now measures it on every push. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_017ULiWeodALX2ZQiLKvTw25
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Adds
.github/workflows/ci.ymlwith six jobs on every push/PR:-DNDEBUGAlso fixes a genuine harness-side data race TSan would have caught: the test allocation counters are now
std::atomic(worker threads allocate contexts during concurrent-build tests).🤖 Generated with Claude Code
https://claude.ai/code/session_017ULiWeodALX2ZQiLKvTw25