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Hadleeraj/README.md

Hi, I'm Hadlee 👋

Computer Engineering MS student at UT Dallas focused on hardware design verification. I build SystemVerilog/UVM testbenches and take designs from RTL through synthesis and physical implementation.

🎯 Seeking: full-time Design Verification / RTL roles and internships (graduating May 2027)

🔬 Currently: independent study on design and verification of an INT8 systolic-array AI accelerator

Verification

  • YAPP Router UVM Verification — three-channel packet router; reusable agents, constrained-random traffic, HBUS sequences, scoreboarding
  • UART UVM Verification — loopback testbench with constrained-random sequences, transaction scoreboard, 100% functional coverage

Design & Implementation

Skills & Tools

Area Tools
Verification SystemVerilog, UVM, constrained-random stimulus, functional coverage, scoreboarding
Simulation Cadence Xcelium, Synopsys VCS, EDA Playground
Design & Synthesis Verilog RTL, Cadence Genus
Physical Design Cadence Innovus, place & route, RC/parasitic analysis
DFT & Test Scan insertion, BIST, ATPG — Synopsys DFT Compiler, TestMAX ATPG, Cadence Modus
Scripting Tcl (P&R automation)
PDKs ASAP7 (7nm FinFET), GF 65nm CMOS

📫 LinkedIn

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  1. YAPP-Router-UVM-Verification YAPP-Router-UVM-Verification Public

    SystemVerilog/UVM verification of a three-channel YAPP packet router: reusable agents, constrained-random traffic, HBUS sequences, and queue-based scoreboarding.

    SystemVerilog

  2. UART-UVM-Verification UART-UVM-Verification Public

    SystemVerilog/UVM UART loopback verification with constrained-random sequences, a transaction scoreboard, and functional coverage.

    SystemVerilog 1

  3. 65nm-CMOS-Standard-Cell-Library 65nm-CMOS-Standard-Cell-Library Public

    Custom standard-cell design, characterization, and 32-bit ALU implementation in GF 65 nm CMOS.

    Verilog

  4. 7nm-FinFET-Standard-Cell-Library 7nm-FinFET-Standard-Cell-Library Public

    7 nm FinFET standard-cell library, registered 3-bit arithmetic unit, synthesis artifacts, and physical-design reports.

    Verilog

  5. MSDAP-ASAP7-ASIC MSDAP-ASAP7-ASIC Public

    Mini Stereo Digital Audio Processor taken RTL-to-GDSII on ASAP7 7 nm: stereo Verilog RTL, SRAM integration, Genus synthesis, Innovus implementation, and verification docs.

    Verilog