I'm a B.Tech student at LPU who took the hardware path — while everyone else chases full-stack frameworks, I chase setup time violations.
Domain : VLSI Design & Verification
Languages : Verilog · SystemVerilog · VHDL · C · C++ · Java
Protocols : AMBA AHB · AMBA APB · SPI · I2C · UART
Toolchain : Xilinx Vivado · Cadence Virtuoso · Spring Boot · MySQL
Currently : Building UVM testbenches that catch bugs before tape-out
Fun fact : I've written more testbenches than test cases — and I'm proud of it|
⚙️ RTL Design 100+ digital circuits in Verilog — adders, FIR filters, alarm clocks, FSMs. If it has flip-flops, it's probably in a repo below. 🔍 IP Verification Constrained-random stimulus, functional coverage, scoreboards — the full UVM stack. Verified APB-based controllers and dual-port RAMs end-to-end. 🌉 Protocol Design Built an AHB-to-APB bridge from scratch, because protocols don't bridge themselves. |
🔬 CMOS Circuits A Mealy machine sequence detector in 90nm CMOS and a VCO-based ADC, simulated entirely in Cadence Virtuoso. 🎛️ FPGA An audio equalizer implemented in VHDL on FPGA — proof that hardware can groove too. 💻 Software When I need a break from waveforms, I build full-stack apps in Java + Spring Boot. Versatility isn't a weakness. |
Hardware Description Languages
Programming
VLSI Domains
Protocols
Tools & Platforms
⚠️ This image goes live only after you add the workflow file below and it runs once. See the setup notes under the code block.
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║ "Software engineers have stack overflow. ║
║ I have timing violations at 3 AM." ║
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║ — Eswar, probably after tape-out ║
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If you've scrolled this far, you should probably just hire me. 🤝