Digital Design & Verification Engineer · MSc Computer Engineering (Embedded Systems), Politecnico di Torino
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What stands in the way, becomes the way
I work on RTL implementation of arithmetic and processor datapaths, functional verification in SystemVerilog/UVM, and taking designs through synthesis, static timing and place-and-route while measuring area, timing and power. My approach is systematic: I build several optimized versions of a design, measure each under the same constraints, and compare them by exploring the design space and plotting the Pareto front.
On the verification side I write SystemVerilog/UVM testbenches with reference-model scoreboards, functional coverage and RAL, and reuse them on the synthesized netlist. Code coverage on the windowed register file is what exposed a bug in its window-overflow logic.
I also write embedded firmware: bare-metal STM32 code at register level without HAL, a four-node wireless sensor network, and FPGA logic that sends commands to the microcontroller.
I'm based in Turin and looking for internships and junior positions in FPGA and ASIC design and verification, available from February 2027.
 Radix-4 Booth Multiplier Signed 32×32 multiplier in structural VHDL on Nangate45 (45 nm), refined from behavioural Booth through Wallace and Dadda trees to a fused selector. Every version synthesized, placed, routed and compared with Design Compiler's own A * B reference.19% smaller, 13% faster, 21% more energy-efficient than the behavioural start; within 0.02 ns of DesignWare latency after layout (1.51 vs 1.49 ns). VHDL · Synopsys Design Compiler · Cadence Innovus |
 5-Stage Pipelined DLX Processor 32-bit DLX CPU in VHDL with branch prediction, forwarding, a pipelined Booth/Dadda multiplier, sub-word memory operations and exceptions. Eight RTL revisions (V0–V7) studied for clock period: 336 Design Compiler runs, every netlist verified at gate level with 24 assembly programs. Fastest version closes at 1.41 ns (709 MHz). VHDL · Synopsys Design Compiler · Python |
 UVM Verification SystemVerilog/UVM environments for a registered 32-bit P4 (parallel-prefix) adder and a 64-bit windowed register file, with architecture-aware functional coverage, a RAL backdoor model, and reuse on the post-synthesis netlist. 100% functional coverage on both (117/117 and 69/69 bins); code coverage exposed a window-overflow defect in the register file. SystemVerilog · UVM · RAL · Questa |
 SHA-256 Synthesis & Power Optimization Baseline vs clock gating vs clock gating + Multi-VT on a 65 nm library at 500 MHz. The RTL is the open-source Secworks core; the flow, constraints, optimization configurations and PPA analysis are my work. Clock gating cut area by 26% and dynamic power by 25%; Multi-VT cut leakage by 84% against baseline, all at timing closure. Synopsys Design Compiler · PrimeTime · TCL |
 Light-Controlled Fan, Register-Level STM32 + FPGA Bare-metal STM32L4 firmware with its own clock, GPIO, USART, SPI, I²C and timer drivers. A 16-bit I²C ADC reads a photoresistor and sets a 20 kHz PWM motor stage; samples are logged to SPI flash with CRC-checked records. A VHDL UART on a Cyclone IV FPGA is the command interface. No HAL: every peripheral configured through its registers. C (bare-metal) · VHDL · STM32L4 · Cyclone IV |
 Capacitive Sensor Sync BSc final project (supervisor: Prof. M. T. Lazarescu). A 4-node wireless capacitive sensor network for presence detection: STM32L412KB nodes with XBee 802.15.4 radios and a MATLAB coordinator that broadcasts one request, with time-slotted replies to avoid collisions. Synchronized 4-node readings, with drift cancellation (IEEE Sensors Journal, 2022) computed on each node. C (bare-metal) · STM32 · XBee · MATLAB |
- Montgomery Serial Multiplier: bit-serial modular multiplier in VHDL (FSMD), comparing behavioural and structural P4-adder datapaths. In progress.
- VHDL Digital Design: FPGA lab designs on the DE1-SoC: adders, multipliers, counters, FSMs.
- MATLAB Signal Processing: communication-system simulation with notch and Bessel filtering and AM multiplexing; up to 37.6 dB SIR.
| HDL | VHDL, SystemVerilog, Verilog | Low power | Clock gating, Multi-VT, activity-based power |
| Verification | UVM, SVA, constrained-random, coverage | Embedded | Bare-metal C, STM32, register-level drivers |
| Synthesis & STA | Synopsys Design Compiler, PrimeTime | Simulation | QuestaSim/ModelSim, GHDL |
| Physical design | Cadence Innovus | Scripting | TCL, Python, Bash |