[Add] Parameterizable decoder and verification flows

.github/workflows/rtl-simulation.yml

@@ -155,7 +155,7 @@ jobs:
           printf 'SKIP\n' > "${openroad_dir}/status.txt"
 
       - name: Qualify representative functional and structural coverage
-        if: (matrix.module == 'write_gate' && matrix.profile == 'width_2') || (matrix.module == 'operand_isolation' && matrix.profile == 'width_16_pattern')
+        if: (matrix.module == 'write_gate' && matrix.profile == 'width_2') || (matrix.module == 'operand_isolation' && matrix.profile == 'width_16_pattern') || (matrix.module == 'decoder' && matrix.profile == 'outputs_3')
         run: |
           set -o pipefail
           module="${{ matrix.module }}"
@@ -176,6 +176,8 @@ jobs:
             export RELEASE_ADDITIONAL_EVIDENCE="reports/write_gate/width_2/coverage_qualification/forced-status.txt reports/write_gate/width_2/openroad/evidence.json reports/write_gate/width_2/openroad/forced-status.txt"
           elif [[ "${{ matrix.module }}" == operand_isolation && "${{ matrix.profile }}" == width_16_pattern ]]; then
             export RELEASE_ADDITIONAL_EVIDENCE="reports/operand_isolation/width_16_pattern/coverage_qualification/forced-status.txt"
+          elif [[ "${{ matrix.module }}" == decoder && "${{ matrix.profile }}" == outputs_3 ]]; then
+            export RELEASE_ADDITIONAL_EVIDENCE="reports/decoder/outputs_3/coverage_qualification/forced-status.txt"
           fi
           make MODULE="${{ matrix.module }}" PROFILE="${{ matrix.profile }}" release-manifest release-manifest-validate 2>&1 | tee ci-artifacts/native-release-manifest.log
 
@@ -278,7 +280,7 @@ jobs:
             2>&1 | tee ci-artifacts/container-flow.log
 
       - name: Qualify representative functional and structural coverage in container
-        if: (matrix.module == 'write_gate' && matrix.profile == 'width_2') || (matrix.module == 'operand_isolation' && matrix.profile == 'width_16_pattern')
+        if: (matrix.module == 'write_gate' && matrix.profile == 'width_2') || (matrix.module == 'operand_isolation' && matrix.profile == 'width_16_pattern') || (matrix.module == 'decoder' && matrix.profile == 'outputs_3')
         run: |
           set -o pipefail
           module="${{ matrix.module }}"
@@ -301,6 +303,8 @@ jobs:
             additional_evidence="reports/write_gate/width_2/coverage_qualification/forced-status.txt"
           elif [[ "${{ matrix.module }}" == operand_isolation && "${{ matrix.profile }}" == width_16_pattern ]]; then
             additional_evidence="reports/operand_isolation/width_16_pattern/coverage_qualification/forced-status.txt"
+          elif [[ "${{ matrix.module }}" == decoder && "${{ matrix.profile }}" == outputs_3 ]]; then
+            additional_evidence="reports/decoder/outputs_3/coverage_qualification/forced-status.txt"
           fi
           docker run --rm \
             --user "$(id -u):$(id -g)" \

README.md

@@ -20,6 +20,7 @@ repository infrastructure and pinned [`mosaic-flow`](mosaic-flow) methodology.
 | `retention_register` | Parameterizable visible state with explicit save and restore behavior | [`docs/retention_register/`](docs/retention_register/) |
 | `write_gate` | Parameterizable architectural suppression of per-bit write enables | [`docs/write_gate/`](docs/write_gate/) |
 | `operand_isolation` | Parameterizable architectural clamping of inactive datapath operands | [`docs/operand_isolation/`](docs/operand_isolation/) |
+| `decoder` | Parameterizable binary-to-one-hot decoder with validity reporting | [`docs/decoder/`](docs/decoder/) |
 
 The authoritative module list used by local automation and the GitHub Actions
 matrix is [`config/modules.json`](config/modules.json). Parameterized modules

config/coverage-policies/decoder.json

@@ -0,0 +1,31 @@
+{
+    "schema": "mosaic-coverage-policy-v1",
+    "scope": {
+        "include": [
+            "rtl/decoder.sv",
+            "verif/coverage/decoder_coverage.sv",
+            "verif/coverage/decoder_transition_coverage.sv"
+        ],
+        "exclude": []
+    },
+    "thresholds": {
+        "line": 95,
+        "branch": 90,
+        "toggle": 90,
+        "user": 100
+    },
+    "coverpoints": [
+        {"name": "disabled_operation", "minimum_hits": 1},
+        {"name": "enabled_legal", "minimum_hits": 1},
+        {"name": "first_selection", "minimum_hits": 1},
+        {"name": "last_selection", "minimum_hits": 1},
+        {"name": "any_output_selected", "minimum_hits": 1},
+        {"name": "enable_asserted", "minimum_hits": 1},
+        {"name": "enable_deasserted", "minimum_hits": 1},
+        {"name": "legal_selection_changed", "minimum_hits": 1},
+        {"name": "legal_to_invalid", "minimum_hits": 1},
+        {"name": "invalid_to_legal", "minimum_hits": 1}
+    ],
+    "exclusions": [],
+    "formal": {"required": true}
+}

config/modules.json

@@ -11,6 +11,7 @@
         {"name": "isolation_cell"},
         {"name": "retention_register"},
         {"name": "write_gate"},
-        {"name": "operand_isolation"}
+        {"name": "operand_isolation"},
+        {"name": "decoder"}
     ]
 }

config/modules/decoder-flows.mk

@@ -0,0 +1,36 @@
+# Required portable checks for the technology-independent decoder leaf.
+FLOW_verible_lint := enabled
+FLOW_verible_format := enabled
+FLOW_slang_elaboration := enabled
+FLOW_verilator_lint := enabled
+FLOW_yosys_synthesis := enabled
+FLOW_symbiyosys_formal := enabled
+FLOW_eqy_equivalence := enabled
+FLOW_verilator_sim := enabled
+FLOW_coverage_qualification := enabled
+FLOW_negative_qualification := enabled
+FLOW_four_state_qualification := enabled
+FLOW_static_intent := enabled
+
+# Clock-domain, scan, power-domain, mapped timing, power, and placement context
+# belong to the first consuming block that uses the decoded controls.
+FLOW_openroad := disabled
+FLOW_vcs_sim := disabled
+FLOW_pyuvm_open_source := disabled
+FLOW_pyuvm_commercial := disabled
+FLOW_vc_lint := disabled
+FLOW_vc_cdc := disabled
+FLOW_sg_cdc := disabled
+FLOW_sg_dft := disabled
+FLOW_vc_lp := disabled
+FLOW_synopsys_synthesis := disabled
+FLOW_synopsys_primetime := disabled
+FLOW_synopsys_primepower := disabled
+
+FLOW_DEPENDENCIES_eqy_equivalence := yosys_synthesis
+FLOW_DEPENDENCIES_coverage_qualification := verilator_sim
+FLOW_DEPENDENCIES_negative_qualification :=
+FLOW_DEPENDENCIES_four_state_qualification :=
+FLOW_DEPENDENCIES_static_intent :=
+FLOW_DEPENDENCIES_synopsys_primetime :=
+FLOW_DEPENDENCIES_synopsys_primepower :=

config/modules/decoder.mk

@@ -0,0 +1,57 @@
+# Decoder tops and design-owned flow inputs.
+export DESIGN_TOP := decoder
+export TB_TOP := $(DESIGN_TOP)_tb
+export FORMAL_TOP := $(DESIGN_TOP)_formal
+export DUT_INSTANCE := $(TB_TOP)/u_unit/dut
+
+export FLOW_CONFIG_ROOT := $(MODULE_ROOT)/flows
+export RTL_FILELIST := $(call resolve_filelist,rtl.f)
+export TB_FILELIST := $(call resolve_filelist,tb.f)
+export FORMAL_FILELIST := $(call resolve_filelist,formal.f)
+export PROPERTY_FILELIST := $(call resolve_filelist,properties.f)
+export ASSERTION_FILELIST := $(call resolve_filelist,assertions.f)
+export COVERAGE_FILELIST := $(call resolve_filelist,coverage.f)
+export VERILATOR_WAIVER_FILE := $(FLOW_CONFIG_ROOT)/verilator_lint/waivers.vlt
+export VERIBLE_WAIVER_FILE := $(FLOW_CONFIG_ROOT)/verible/waivers.txt
+export VERIBLE_RULES_FILE := $(FLOW_CONFIG_ROOT)/verible/rules
+export VERIBLE_FORMAT_ARGS := --indentation_spaces=4
+export VERIBLE_FORMAT_PATHS := \
+    rtl/decoder.sv \
+    verif/properties/decoder_predicates.svh \
+    verif/assertions/decoder_sva.sv \
+    verif/assertions/decoder_bind.sv \
+    verif/coverage/decoder_coverage.sv \
+    verif/coverage/decoder_transition_coverage.sv \
+    verif/coverage/decoder_coverage_bind.sv \
+    verif/formal/decoder_formal.sv \
+    verif/mutations/decoder_inverted_enable_mutant.sv \
+    verif/tb/decoder_test_case.sv \
+    verif/tb/decoder_tb.sv \
+    verif/tb/decoder_four_state_tb.sv \
+    verif/tb/decoder_invalid_num_outputs_tb.sv \
+    verif/tb/decoder_invalid_select_width_tb.sv
+export FORMAL_CONFIG := $(call resolve_flow_config,symbiyosys,formal.sby)
+export FORMAL_COVER_CONFIG := $(MODULE_ROOT)/flows/symbiyosys/decoder.cover.sby
+export EQUIVALENCE_CONFIG := $(call resolve_flow_config,eqy,equivalence.eqy)
+export COVERAGE_QUALIFICATION_POLICY := $(MODULE_ROOT)/config/coverage-policies/decoder.json
+export COVERAGE_QUALIFICATION_SOURCE := verilator_sim
+export SIM_COVERAGE := enabled
+export QUALIFICATION_CAMPAIGN_MANIFEST := $(MODULE_ROOT)/config/qualification-campaigns/decoder.json
+export STATIC_INTENT_CONFIG := $(MODULE_ROOT)/config/static-intent/decoder.json
+export OPENROAD_CONFIG := $(call resolve_flow_config,openroad,config.mk)
+export SYNTHESIS_CONSTRAINT_FILE := $(call resolve_flow_config,synthesis,timing.sdc)
+export ASYNC_SYNTHESIS_CONSTRAINT_FILE :=
+export OPENROAD_CONSTRAINT_FILE := $(MODULE_ROOT)/flows/openroad/decoder.timing.sdc
+export CDC_CONFIG := $(call resolve_flow_config,cdc,constraints.tcl)
+export DFT_CONFIG := $(call resolve_flow_config,sg_dft,constraints.tcl)
+export UPF_CONFIG := $(call resolve_flow_config,vc_lp,power.upf)
+export CONSTRAINT_DIR := $(FLOW_CONFIG_ROOT)/synthesis
+
+export REPORT_DIR := $(MODULE_ROOT)/reports/$(MODULE)
+export WORK_DIR := $(MODULE_ROOT)/work/$(MODULE)
+export OPENROAD_PLATFORM ?= nangate45
+export TECH_SETUP_TCL ?=
+export TARGET_LIBRARY ?=
+export LINK_LIBRARY ?=
+export OPERATING_CONDITION ?=
+export ACTIVITY_FILE ?=$(WORK_DIR)/vcs_sim/$(DESIGN_TOP).saif

config/parameter-profiles/decoder.json

@@ -0,0 +1,53 @@
+{
+    "schema": "mosaic-parameter-profiles-v1",
+    "include": [
+        {
+            "name": "outputs_1",
+            "parameters": {"NUM_OUTPUTS": 1},
+            "flows": ["verible_lint", "verible_format", "slang_elaboration", "verilator_lint", "yosys_synthesis", "symbiyosys_formal", "eqy_equivalence", "verilator_sim", "negative_qualification", "four_state_qualification", "static_intent"],
+            "tops": {"design": "decoder", "testbench": "decoder_tb", "formal": "decoder_formal"}
+        },
+        {
+            "name": "outputs_2",
+            "parameters": {"NUM_OUTPUTS": 2},
+            "flows": ["verible_lint", "verible_format", "slang_elaboration", "verilator_lint", "yosys_synthesis", "symbiyosys_formal", "eqy_equivalence", "verilator_sim", "static_intent"],
+            "tops": {"design": "decoder", "testbench": "decoder_tb", "formal": "decoder_formal"}
+        },
+        {
+            "name": "outputs_3",
+            "parameters": {"NUM_OUTPUTS": 3},
+            "flows": ["verible_lint", "verible_format", "slang_elaboration", "verilator_lint", "yosys_synthesis", "symbiyosys_formal", "eqy_equivalence", "verilator_sim", "static_intent"],
+            "tops": {"design": "decoder", "testbench": "decoder_tb", "formal": "decoder_formal"}
+        },
+        {
+            "name": "outputs_4",
+            "parameters": {"NUM_OUTPUTS": 4},
+            "flows": ["verible_lint", "verible_format", "slang_elaboration", "verilator_lint", "yosys_synthesis", "symbiyosys_formal", "eqy_equivalence", "verilator_sim", "static_intent"],
+            "tops": {"design": "decoder", "testbench": "decoder_tb", "formal": "decoder_formal"}
+        },
+        {
+            "name": "outputs_5",
+            "parameters": {"NUM_OUTPUTS": 5},
+            "flows": ["verible_lint", "verible_format", "slang_elaboration", "verilator_lint", "yosys_synthesis", "symbiyosys_formal", "eqy_equivalence", "verilator_sim", "static_intent"],
+            "tops": {"design": "decoder", "testbench": "decoder_tb", "formal": "decoder_formal"}
+        },
+        {
+            "name": "outputs_8",
+            "parameters": {"NUM_OUTPUTS": 8},
+            "flows": ["verible_lint", "verible_format", "slang_elaboration", "verilator_lint", "yosys_synthesis", "symbiyosys_formal", "eqy_equivalence", "verilator_sim", "static_intent"],
+            "tops": {"design": "decoder", "testbench": "decoder_tb", "formal": "decoder_formal"}
+        },
+        {
+            "name": "outputs_16",
+            "parameters": {"NUM_OUTPUTS": 16},
+            "flows": ["verible_lint", "verible_format", "slang_elaboration", "verilator_lint", "yosys_synthesis", "symbiyosys_formal", "eqy_equivalence", "verilator_sim", "static_intent"],
+            "tops": {"design": "decoder", "testbench": "decoder_tb", "formal": "decoder_formal"}
+        },
+        {
+            "name": "outputs_32",
+            "parameters": {"NUM_OUTPUTS": 32},
+            "flows": ["verible_lint", "verible_format", "slang_elaboration", "verilator_lint", "yosys_synthesis", "symbiyosys_formal", "eqy_equivalence", "verilator_sim", "static_intent"],
+            "tops": {"design": "decoder", "testbench": "decoder_tb", "formal": "decoder_formal"}
+        }
+    ]
+}