Akshad2911

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Akshad Dhamande Akshad2911

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Aspiring VLSI Engineer • Verilog • RTL Design • FPGA • Digital IC Design

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Akshad2911/README.md

VLSI Design Engineer | RTL Design | Physical Design | FPGA Development

🔬 Verilog • SystemVerilog • Cadence Virtuoso • CMOS Design • SRAM • Digital IC Design

I'm an Electronics & Communication Engineering student passionate about VLSI, Digital Design, FPGA, and Embedded Systems.

🔧 Hands-on experience with ESP32, Arduino, Raspberry Pi & FPGA
💻 Skilled in Verilog, SystemVerilog, FSM Design & RTL Development
🧠 Designing 6T, 8T & 10T SRAM cells using Cadence Virtuoso
⚡ Experienced in Analog IC Design, Layout, DRC, LVS & PEX Verification
👟 Developed a Smart Shoe for Real-Time Gait Analysis
🚀 Passionate about Semiconductor Technology, ISRO, NASA & Space Systems

I enjoy turning ideas into working prototypes and explaining systems through design.

🛠️ Tech Stack

🧠 Languages & Tools

💻 Programming Languages

⚡Hardware Description Languages (HDLs)

🛠️ VLSI & EDA Tools

🔬 Digital Design & Verification

🔧 Hardware Platforms

📡 Communication Protocols

🚀 Projects

⚡ Implementation and Verification of OTA & Schmitt Trigger

Designed and simulated OTA & Schmitt Trigger circuits in Cadence Virtuoso
Completed schematic design, layout implementation & circuit verification
Performed AC analysis, DRC, LVS, PEX & GDSII generation
Gained hands-on experience in analog CMOS circuit design and validation

🧠 SRAM Design (Major Project)

Designed and analyzed 6T, 8T & 10T SRAM cells using Cadence Virtuoso
Evaluated read/write stability, power consumption & performance
Performed schematic design, layout implementation & circuit verification
Conducted DRC, LVS, PEX and post-layout simulations for design validation

🧮 PS/2 Keyboard Based ALU (FPGA)

Designed an FSM-based ALU in Verilog with PS/2 keyboard interface
Supports addition, subtraction & multiplication of single-digit inputs
Displays real-time results on dual 7-segment displays
Verified functionality through simulation and FPGA implementation

📈 GitHub Stats

✍️ Random Dev Quote

🌐 Let’s Connect

⭐ If you like my work, consider starring my repositories
🚀 Always learning. Always building.

Popular repositories Loading

Nand-Gate Nand-Gate Public

A simple Verilog implementation of a NAND gate with simulation testbench and waveform outputs. Ideal for beginners learning digital logic and HDL design.

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SRAM-Design-and-Verification-using-SystemVerilog SRAM-Design-and-Verification-using-SystemVerilog Public

This project implements a Static Random Access Memory (SRAM) using SystemVerilog, supporting synchronous read and write operations. The design is verified using a SystemVerilog testbench to ensure …

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Verilog_Logic_Gates Verilog_Logic_Gates Public

A beginner-friendly Verilog HDL repository featuring implementations of fundamental logic gates with truth tables, testbenches, and simulation waveforms, helping users learn digital logic design, F…

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Verilog_Mux_Demux Verilog_Mux_Demux Public

Verilog HDL code library for beginners containing 2x1, 4x1, and 8x1 multiplexers, as well as 1x4 demultiplexer, along with their truth tables and simulation waveforms.

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Verilog_Converters Verilog_Converters Public

An easy-to-understand Verilog HDL source code repository that includes Encoders, Decoders, and Comparators, complete with truth tables and simulation waveforms. Suitable for learning digital logic …

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