Issues

• Avoiding names that are already defined by python and so cannot be used to name a ROM.

  VLSIDA/OpenRAM#312 · Filter by author philiprbrenan opened on Sep 9, 2026
  4

• Gnerating a ROM with 6*1 works but 4*1 does not

  VLSIDA/OpenRAM#307 · Filter by author philiprbrenan opened on Sep 4, 2026
  2

• Generated Liberty sets input-pin max_transition (0.04 ns) below the PDK's achievable slew

  VLSIDA/OpenRAM#298 · Filter by author cpehle opened on Jul 17, 2026
  4

• Incorrect internal_power values in generated SKY130 Liberty files

  VLSIDA/OpenRAM#294 · Filter by author Blueonics opened on Apr 30, 2026
  2

• LVS mismatch errors with Sky130 PDK

  VLSIDA/OpenRAM#292 · Filter by author gumnaam2 opened on Apr 19, 2026
  11

• sky130 PEX fails due to missing storage node labels in bitcell_2port

  VLSIDA/OpenRAM#281 · Filter by author DashCodeHub opened on Feb 2, 2026
  2

• For sky130, in the generated .lef file, the value of 'DATABASE MICRONS' is wrong.

  VLSIDA/OpenRAM#278 · Filter by author ManzoniGiuseppe opened on Dec 16, 2025
  

• FreePDK45 Control Logic Timing - Glitches or Expected Behavior?

  VLSIDA/OpenRAM#276 · Filter by author buchtawill opened on Oct 18, 2025
  1

• Sense amp enable timing error when generating 1 Kb (1024 bits) SRAM — requires manual delay chain adjustment

  VLSIDA/OpenRAM#274 · Filter by author cyberxcodes opened on Oct 16, 2025
  1

• ImportError: Missing 'lef_rom_interconnect' in stable version's OpenRAM tech module

  VLSIDA/OpenRAM#273 · Filter by author OsFlora opened on Aug 18, 2025
  4

  

• Please consider switching from volare to ciel

  VLSIDA/OpenRAM#269 · Filter by author hpretl opened on Jun 26, 2025
  2

• Generating SRAM fails at supply_router: Couldn't route from (vdd layer=m3 ...) to to (vdd layer=m3 ...)

  VLSIDA/OpenRAM#268 · Filter by author kammoh opened on May 14, 2025
  2

• Documentation clarifications in basic_usage and basic_setup

  VLSIDA/OpenRAM#262 · Filter by author sampollard opened on Feb 26, 2025
  1

• macro - <ROM instance> does not contain any shapes or vias

  VLSIDA/OpenRAM#254 · Filter by author tvd040562 opened on Sep 24, 2024

• ROM simulation model using $readmemb for binary file will NOT work

  VLSIDA/OpenRAM#253 · Filter by author tvd040562 opened on Sep 24, 2024

• Assertion Error in SRAM Generation with Specific word_size and num_words Configurations

  VLSIDA/OpenRAM#251 · Filter by author riagus99 opened on Aug 18, 2024
  12

• Generating SRAM gets stuck in extraction process of magic

  VLSIDA/OpenRAM#248 · Filter by author FriedrichWu opened on Jul 30, 2024
  4

• Error in using sram macro(tiny) in openlane2

  VLSIDA/OpenRAM#247 · Filter by author FriedrichWu opened on Jul 19, 2024
  3

• Runtime

  VLSIDA/OpenRAM#245 · Filter by author mbautista-lab opened on Jun 25, 2024
  8

• Possible minor error on the documentation related with the ROM usage

  VLSIDA/OpenRAM#243 · Filter by author PabloUlises opened on May 31, 2024

• Power estimation seems too high

  VLSIDA/OpenRAM#242 · Filter by author LucaMartis00 opened on May 24, 2024
  14

• Errors hidden on default loglevel, but visible on verbose loglevels.

  VLSIDA/OpenRAM#240 · Filter by author c-93 opened on May 3, 2024

• Question: What is the correct allignment in SKY130? Intermediate Pins are not connected to the grid. Likely user mistake.

  VLSIDA/OpenRAM#239 · Filter by author c-93 opened on Apr 29, 2024
  10

• Routing error due to high (vertical) density?

  enhancementhelp wanted
  VLSIDA/OpenRAM#236 · Filter by author c-93 opened on Apr 15, 2024
  1

• Stimuli Generation - sram_func.py or gen_stimuli.py

  VLSIDA/OpenRAM#234 · Filter by author abdullahsahruri opened on Apr 10, 2024